| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-05-21 | restructured project | Flavian Kaufmann | |
| 2024-05-21 | alu graphic | Flavian Kaufmann | |
| 2024-05-21 | updated README | Flavian Kaufmann | |
| 2024-05-21 | mixed up riscv tables in README | Flavian Kaufmann | |
| 2024-05-21 | rv32 documentation | Flavian Kaufmann | |
| 2024-05-21 | cleaned up graphics | Flavian Kaufmann | |
| 2024-05-20 | fixed typo | Flavian Kaufmann | |
| 2024-05-20 | added some graphics | Flavian Kaufmann | |
| 2024-05-20 | reset synchronizer | Flavian Kaufmann | |
| 2024-05-20 | io | Flavian Kaufmann | |
| 2024-05-20 | nextpnr himbaechel | Flavian Kaufmann | |
| 2024-05-15 | fixed relative memory addressing bug | Flavian Kaufmann | |
| 2024-05-15 | running c program | Flavian Kaufmann | |
| 2024-05-14 | bug fixes | Flavian Kaufmann | |
| 2024-05-14 | declaration before use | Flavian Kaufmann | |
| 2024-05-13 | refactored fsm output logic | Flavian Kaufmann | |
| 2024-05-13 | refactoring constants | Flavian Kaufmann | |
| 2024-05-13 | async reset | Flavian Kaufmann | |
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann | |
| 2024-05-12 | refactoring | Flavian Kaufmann | |
| 2024-05-09 | stopped initializing ram and register file to 0 at beginning | Flavian Kaufmann | |
| 2024-05-09 | added remaining branch instructions | Flavian Kaufmann | |
| 2024-05-09 | fixed sw bug, where we wasn't set correctly | Flavian Kaufmann | |
| 2024-05-09 | added jalr instruction | Flavian Kaufmann | |
| 2024-05-08 | added references | Flavian Kaufmann | |
| 2024-05-08 | Updated Readme with tool information | Flavian Kaufmann | |
| 2024-05-08 | waveform example | Flavian Kaufmann | |
| 2024-05-08 | view cpu waveform with make wave | Flavian Kaufmann | |
| 2024-05-08 | updated readme for make rom | Flavian Kaufmann | |
| 2024-05-08 | build assembly files | Flavian Kaufmann | |
| 2024-05-08 | fixed bug where register addresses were used instead of data | Flavian Kaufmann | |
| 2024-05-08 | assemble simple rom | Flavian Kaufmann | |
| 2024-05-08 | alu op decode | Flavian Kaufmann | |
| 2024-05-07 | alu equal | Flavian Kaufmann | |
| 2024-05-07 | control unit | Flavian Kaufmann | |
| 2024-05-07 | cpu | Flavian Kaufmann | |
| 2024-05-06 | added cpu | Flavian Kaufmann | |
| 2024-05-05 | genrom | Flavian Kaufmann | |
| 2024-05-05 | initialize rom to rom/rom.hex | Flavian Kaufmann | |
| 2024-05-05 | added memory unit | Flavian Kaufmann | |
| 2024-05-05 | added info to view waveform with gtkwave to readme | Flavian Kaufmann | |
| 2024-05-05 | register file testbench | Flavian Kaufmann | |
| 2024-05-05 | added register file | Flavian Kaufmann | |
| 2024-05-04 | renamed some signals | Flavian Kaufmann | |
| 2024-05-04 | updated README.md for new Makefile | Flavian Kaufmann | |
| 2024-05-04 | added support for multiple testbenches | Flavian Kaufmann | |
| 2024-05-02 | register file | Flavian Kaufmann | |
| 2024-05-02 | cleaned test output | Flavian Kaufmann | |
| 2024-05-01 | fixed unsigned not recognized in verilog 2000 bug | Flavian Kaufmann | |
| 2024-05-01 | added make target for testvec generation | Flavian Kaufmann | |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |