41 files changed, 298 insertions, 187 deletions
diff --git a/Makefile b/Makefile
index e5a37b7..3087ffa 100644
--- a/Makefile
+++ b/Makefile
@@ -1,171 +1,61 @@
-PRJ_NAME = riscv_cpu
-TOP_MODULE = top
-
-# Directories
-SRC_DIR = src
-SIM_DIR = sim
-GENTESTVEC_DIR = gentestvec
-CST_DIR = cst
 BUILD_DIR = build
 
-# Source Files
-SRC_FILES = $(wildcard $(SRC_DIR)/*.v)
-SIM_FILES = $(wildcard $(SIM_DIR)/testbench_*.v)
-GENTESTVEC_FILES = $(wildcard $(GENTESTVEC_DIR)/gentestvec_*.c)
-CST_FILES = $(wildcard $(CST_DIR)/*.cst)
+# dirs
+PROG_DIR = prog
+GENTESTVEC_DIR = sim/gentestvec
+TESTBENCH_DIR = sim/testbenches
+RTL_DIR = rtl
 
-# Output Files
-SIM_EXECUTABLES = $(patsubst $(SIM_DIR)/testbench_%.v, $(BUILD_DIR)/testbench_%,$(SIM_FILES))
-GENTESTVEC_EXECUTABLES = $(patsubst $(GENTESTVEC_DIR)/gentestvec_%.c, $(BUILD_DIR)/gentestvec_%,$(GENTESTVEC_FILES))
-TESTVECTOR_FILES = $(patsubst $(BUILD_DIR)/gentestvec_%, $(BUILD_DIR)/testvec_%.txt, $(GENTESTVEC_EXECUTABLES))
-WAVEFORM_FILES = $(patsubst $(BUILD_DIR)/testbench_%, $(BUILD_DIR)/waveform_%.vcd, $(SIM_EXECUTABLES))
+# tools
+MAKE = make
 
-BITSTREAM = $(BUILD_DIR)/$(PRJ_NAME).fs
+all: simulate
 
-# Programs
-CC = clang
-CFLAGS = -O3
+# generate rom
+rom:
+	$(MAKE) -C $(PROG_DIR) BUILD_DIR=../$(BUILD_DIR) all
 
-IVERILOG = iverilog
-VVP = vvp
-GTKWAVE = gtkwave
+# print objdump of rom
+objdump:
+	$(MAKE) -C $(PROG_DIR) BUILD_DIR=../$(BUILD_DIR) objdump
 
-YOSYS = yosys
-NEXTPNR = nextpnr-himbaechel
-GOWIN_PACK = gowin_pack
-PROGRAMMER = openFPGALoader
+# print size information of rom
+size:
+	$(MAKE) -C $(PROG_DIR) BUILD_DIR=../$(BUILD_DIR) size
 
-FAMILY = GW1N-9C
-DEVICE = GW1NR-LV9QN88PC6/I5
-BOARD = tangnano9k
 
-# RISCV Toolchain
-RISCV_TOOLCHAIN = riscv64-unknown-elf
-RISCV_AS = $(RISCV_TOOLCHAIN)-as
-RISCV_CC = $(RISCV_TOOLCHAIN)-gcc
-RISCV_LD = $(RISCV_TOOLCHAIN)-ld
-RISCV_OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
-RISCV_OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
 
-RISCV_ASFLAGS = -march=rv32i -mabi=ilp32
-RISCV_CFLAGS = -march=rv32i -mabi=ilp32
-RISCV_LDFLAGS = -T prog/link.ld -m elf32lriscv
+# generate testvec files
+testvec:
+	$(MAKE) -C $(GENTESTVEC_DIR) BUILD_DIR=../../$(BUILD_DIR) all
 
-PROG_SOURCE_DIR = prog/src
 
-PROG_ASSEMBLY_SOURCES = $(wildcard $(PROG_SOURCE_DIR)/*.s)
-PROG_C_SOURCES = $(wildcard $(PROG_SOURCE_DIR)/*.c)
-PROG_OBJECT_FILES = $(PROG_ASSEMBLY_SOURCES:$(PROG_SOURCE_DIR)/%.s=$(BUILD_DIR)/%.o) $(PROG_C_SOURCES:$(PROG_SOURCE_DIR)/%.c=$(BUILD_DIR)/%.o)
-PROG_ELF_FILE = $(BUILD_DIR)/prog.elf
-PROG_BINARY_FILE = $(BUILD_DIR)/prog.bin
-PROG_ROM_FILE = $(BUILD_DIR)/rom.hex
 
+# run testbenches (simulate)
+simulate: rom testvec
+	$(MAKE) -C $(TESTBENCH_DIR) BUILD_DIR=../../$(BUILD_DIR) all
+
+# display waveform of cpu testbench
+wave: rom testvec
+	$(MAKE) -C $(TESTBENCH_DIR) BUILD_DIR=../../$(BUILD_DIR) wave
+
+
+
+# generate bitstream
+bitstream: rom
+	$(MAKE) -C $(RTL_DIR) BUILD_DIR=../$(BUILD_DIR) all
+
+# upload bitstream
+upload: rom
+	$(MAKE) -C $(RTL_DIR) BUILD_DIR=../$(BUILD_DIR) upload
+
+# flash bitstream
+flash: rom
+	$(MAKE) -C $(RTL_DIR) BUILD_DIR=../$(BUILD_DIR) flash
 
-all: simulate
 
 
-$(BUILD_DIR)/$(PRJ_NAME).json: $(SRC_FILES) | $(BUILD_DIR)
-	@echo
-	@echo "=================================================="
-	@echo " Synthesizing"
-	@echo "=================================================="
-	$(YOSYS) -p "synth_gowin -top $(TOP_MODULE)" -o $(BUILD_DIR)/$(PRJ_NAME).json $(SRC_FILES)
-	@echo "=================================================="
-	@echo " Completed Synthesis"
-	@echo "=================================================="
-	@echo
-
-$(BUILD_DIR)/$(PRJ_NAME)_pnr.json: $(BUILD_DIR)/$(PRJ_NAME).json $(CST_FILES)
-	@echo
-	@echo "==================================================="
-	@echo " Routing"
-	@echo "==================================================="
-	$(NEXTPNR) --json $(BUILD_DIR)/$(PRJ_NAME).json --write $(BUILD_DIR)/$(PRJ_NAME)_pnr.json --device $(DEVICE) --vopt family=$(FAMILY) --vopt cst=$(CST_FILES)
-	@echo "==================================================="
-	@echo " Completed Routing"	
-	@echo "==================================================="
-	@echo
-
-$(BITSTREAM): $(BUILD_DIR)/$(PRJ_NAME)_pnr.json
-	@echo
-	@echo "==================================================="
-	@echo " Generating Bitstream"
-	@echo "==================================================="
-	$(GOWIN_PACK) -d $(FAMILY) -o $(BITSTREAM) $(BUILD_DIR)/$(PRJ_NAME)_pnr.json
-	@echo "==================================================="
-	@echo " Generated Bitstream"
-	@echo "==================================================="
-	@echo
-
-bitstream: $(BITSTREAM)
-	
-upload: $(BITSTREAM)
-	$(PROGRAMMER) -b $(BOARD) $(BITSTREAM)
-
-flash: $(BITSTREAM)
-	$(PROGRAMMER) -b $(BOARD) -f $(BITSTREAM)
-
-simulate: $(WAVEFORM_FILES)
-
-# Build the testbench executables
-$(BUILD_DIR)/testbench_%: $(SIM_DIR)/testbench_%.v $(SRC_FILES) | $(BUILD_DIR) $(PROG_ROM_FILE)
-	$(IVERILOG) -o $@ $^
-
-# Build the test vector generator executables
-$(BUILD_DIR)/gentestvec_%: $(GENTESTVEC_DIR)/gentestvec_%.c | $(BUILD_DIR)
-	$(CC) $(CFLAGS) -o $@ $<
-
-# Generate the test vector files
-$(BUILD_DIR)/testvec_%.txt: $(BUILD_DIR)/gentestvec_%
-	$< > $@
-
-# Run the simulation and generate the waveform files
-$(BUILD_DIR)/waveform_%.vcd: $(BUILD_DIR)/testbench_% $(BUILD_DIR)/testvec_%.txt
-	@echo
-	@echo "==================================================="
-	@echo " Running Testbench ($*)"
-	@echo "==================================================="
-	$(VVP) $< +testvec=$(BUILD_DIR)/testvec_$*.txt +waveform=$@
-	@echo "==================================================="
-	@echo " Completed Testbench ($*)"
-	@echo "==================================================="
-	@echo
-
-rom: $(PROG_ROM_FILE)
-
-# Assemble assembly source files into object files
-$(BUILD_DIR)/%.o: $(PROG_SOURCE_DIR)/%.s | $(BUILD_DIR)
-	$(RISCV_AS) $(RISCV_ASFLAGS) -o $@ $<
-
-# Compile C source files into object files
-$(BUILD_DIR)/%.o: $(PROG_SOURCE_DIR)/%.c | $(BUILD_DIR)
-	$(RISCV_CC) $(RISCV_CFLAGS) -c -o $@ $<
-
-# Link the object files to create an ELF file
-$(PROG_ELF_FILE): $(PROG_OBJECT_FILES)
-	$(RISCV_LD) $(RISCV_LDFLAGS) -o $@ $^
-
-# Convert the ELF file to a binary file
-$(PROG_BINARY_FILE): $(PROG_ELF_FILE)
-	$(RISCV_OBJCOPY) -O binary $< $@
-
-# Convert the binary file to a hex file
-$(PROG_ROM_FILE): $(PROG_BINARY_FILE)
-	xxd -g 4 -c 4 -p $< | awk '{print substr($$0,7,2) substr($$0,5,2) substr($$0,3,2) substr($$0,1,2)}' > $@
-
-# Create the build directory
-$(BUILD_DIR):
-	mkdir -p $(BUILD_DIR)
-
-wave:
-	$(GTKWAVE) -a debug/cpu.gtkw $(BUILD_DIR)/waveform_cpu.vcd
-
-objdump: $(PROG_ELF_FILE)
-	$(RISCV_OBJDUMP) -d -x --disassembler-color=on $(PROG_ELF_FILE)
-
-# Clean
 clean:
 	rm -rf $(BUILD_DIR)
 
-.PHONY: all simulate rom bitsream upload flash wave objdump clean
-
+.PHONY: all clean rom rom_objdump rom_size testvec simulate wave bitstream upload flash
+\ No newline at end of file
diff --git a/README.md b/README.md
index 75001f9..7f42392 100644
--- a/README.md
+++ b/README.md
@@ -12,15 +12,45 @@ The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardw
 ## Build
 
 * `make all` alias for `make simulate`.
-* `make simulate` to run all the testbenches (sim/testbench_*.v).
-* `make bitstream` to synthesize, place and route the design and to generate the bitstream.
-* `make upload` to upload the bitstream to the FPGA.
-* `make flash` to flash the bitsream to the FPGA.
-* `make clean` to clean build files.
-* `gtkwave build/waveform_*.vcd` to view waveform of corresponding testbench.
-* `make rom` to compile source files in prog/src, link and generate rom file.
-* `make objdump` to disassemble rom file.
-* `make wave` to view waveform of cpu running build/rom.hex.
+* `make rom` to build rom.
+* `make objdump` to disassemble rom.
+* `make size` to display size information of rom.
+* `make testvec` to generate testvectors.
+* `make simulate` to run testbenches.
+* `make wave` to view waveform of cpu testbench in gtkwave.
+* `make bitstream` to generate bitstream.
+* `make upload` to upload bitstream to fpga.
+* `make flash` to flash bitstream to fpga.
+* `make clean` to clean build folder.
+
+## Project Structure
+
+```(txt)
+riscv_cpu
+  |-> build         # build folder
+  |-> debug
+    |-> cpu.gtkw    # template for gtkwave
+  |-> prog
+    |-> include
+    |-> src
+    |-> link.ld
+    |-> Makefile
+  |-> res           # various resources
+  |-> rtl           # rtl sources (verilog files)
+    |-> cst         # constraints file for fpga
+    |-> include
+    |-> src
+    |-> Makefile
+  |-> sim
+    |-> gentestvec  # generate testvectors for testbenches
+      |-> src
+      |-> Makefile
+    |-> testbenches # testbench sources
+      |-> src
+      |-> Makefile
+  |-> Makefile
+  |-> README.md
+```
 
 ## Tools
 
diff --git a/prog/Makefile b/prog/Makefile
new file mode 100644
index 0000000..a5dfeaa
--- /dev/null
+++ b/prog/Makefile
@@ -0,0 +1,65 @@
+BUILD_DIR ?= build
+
+# risc-v toolchain
+RISCV_TOOLCHAIN = riscv64-unknown-elf
+RISCV_AS        = $(RISCV_TOOLCHAIN)-as
+RISCV_CC        = $(RISCV_TOOLCHAIN)-gcc
+RISCV_LD        = $(RISCV_TOOLCHAIN)-ld
+RISCV_OBJCOPY   = $(RISCV_TOOLCHAIN)-objcopy
+RISCV_OBJDUMP   = $(RISCV_TOOLCHAIN)-objdump
+RISCV_SIZE      = $(RISCV_TOOLCHAIN)-size
+
+# assembler / compiler / linker flags
+RISCV_ASFLAGS = -march=rv32i -mabi=ilp32
+RISCV_CFLAGS  = -march=rv32i -mabi=ilp32
+RISCV_LDFLAGS = -T link.ld -m elf32lriscv
+
+# dirs and files
+SOURCE_DIR = src
+AS_SOURCES = $(wildcard $(SOURCE_DIR)/*.s)
+C_SOURCES  = $(wildcard $(SOURCE_DIR)/*.c)
+OBJ_FILES  = $(AS_SOURCES:$(SOURCE_DIR)/%.s=$(BUILD_DIR)/%.o) $(C_SOURCES:$(SOURCE_DIR)/%.c=$(BUILD_DIR)/%.o)
+ELF_FILE   = $(BUILD_DIR)/prog.elf
+BIN_FILE   = $(BUILD_DIR)/prog.bin
+ROM_FILE   = $(BUILD_DIR)/rom.hex
+
+
+# targets
+all: $(ROM_FILE)
+
+# assemble assembly files to object files
+$(BUILD_DIR)/%.o: $(SOURCE_DIR)/%.s | $(BUILD_DIR)
+	$(RISCV_AS) $(RISCV_ASFLAGS) -o $@ $<
+
+# compile source files to object files
+$(BUILD_DIR)/%.o: $(SOURCE_DIR)/%.c | $(BUILD_DIR)
+	$(RISCV_CC) $(RISCV_CFLAGS) -c -o $@ $<
+
+# link object files to elf file
+$(ELF_FILE): $(OBJ_FILES)
+	$(RISCV_LD) $(RISCV_LDFLAGS) -o $@ $^
+
+# create binary file from elf file
+$(BIN_FILE): $(ELF_FILE)
+	$(RISCV_OBJCOPY) -O binary $< $@
+
+# convert binary file hex file
+$(ROM_FILE): $(BIN_FILE)
+	xxd -g 4 -c 4 -p $< | awk '{print substr($$0,7,2) substr($$0,5,2) substr($$0,3,2) substr($$0,1,2)}' > $@
+
+# create build dir
+$(BUILD_DIR):
+	mkdir -p $(BUILD_DIR)
+
+# create objdump of elf file and print
+objdump: $(ELF_FILE)
+	$(RISCV_OBJDUMP) -d -x --disassembler-color=on $(ELF_FILE)
+
+# display size information of elf file
+size: $(ELF_FILE)
+	$(RISCV_SIZE) $(ELF_FILE)
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+.PHONY: all clean objdump size
+\ No newline at end of file
diff --git a/rtl/Makefile b/rtl/Makefile
new file mode 100644
index 0000000..901d81f
--- /dev/null
+++ b/rtl/Makefile
@@ -0,0 +1,56 @@
+BUILD_DIR ?= build
+
+# defines
+TOP_MODULE = top
+PRJ_NAME   = riscv_cpu
+
+# dirs and files
+SRC_DIR   = src
+SOURCES   = $(wildcard $(SRC_DIR)/*.v)
+CST_DIR   = cst
+CST_FILES = $(wildcard $(CST_DIR)/*.cst)
+BITSTREAM = $(BUILD_DIR)/$(PRJ_NAME).fs
+
+# tools
+YOSYS      = yosys
+NEXTPNR    = nextpnr-himbaechel
+GOWIN_PACK = gowin_pack
+PROGRAMMER = openFPGALoader
+
+# fpga
+FAMILY = GW1N-9C
+DEVICE = GW1NR-LV9QN88PC6/I5
+BOARD  = tangnano9k
+
+
+# targets
+all: $(BITSTREAM)
+
+# synthesize
+$(BUILD_DIR)/$(PRJ_NAME).json: $(SOURCES) | $(BUILD_DIR)
+	@echo "read_verilog -Irtl $(SOURCES)"                   > $(BUILD_DIR)/synth_gowin.ys
+	@echo "chparam -set ROM_FILE \"../build/rom.hex\" rom" >> $(BUILD_DIR)/synth_gowin.ys
+	@echo "synth_gowin -top $(TOP_MODULE)"                 >> $(BUILD_DIR)/synth_gowin.ys
+	$(YOSYS) $(BUILD_DIR)/synth_gowin.ys -o $(BUILD_DIR)/$(PRJ_NAME).json
+
+# place and route
+$(BUILD_DIR)/$(PRJ_NAME)_pnr.json: $(BUILD_DIR)/$(PRJ_NAME).json $(CST_FILES)
+	$(NEXTPNR) --json $(BUILD_DIR)/$(PRJ_NAME).json --write $(BUILD_DIR)/$(PRJ_NAME)_pnr.json --device $(DEVICE) --vopt family=$(FAMILY) --vopt cst=$(CST_FILES)
+
+# generate bitstream
+$(BITSTREAM): $(BUILD_DIR)/$(PRJ_NAME)_pnr.json
+	$(GOWIN_PACK) -d $(FAMILY) -o $(BITSTREAM) $(BUILD_DIR)/$(PRJ_NAME)_pnr.json
+
+bitstream: $(BITSTREAM)
+	
+upload: $(BITSTREAM)
+	$(PROGRAMMER) -b $(BOARD) $(BITSTREAM)
+
+flash: $(BITSTREAM)
+	$(PROGRAMMER) -b $(BOARD) -f $(BITSTREAM)
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+.PHONY: all clean bitsream upload flash
+
diff --git a/cst/tangnano9k.cst b/rtl/cst/tangnano9k.cst
index e909e36..e909e36 100644
--- a/cst/tangnano9k.cst
+++ b/rtl/cst/tangnano9k.cst
diff --git a/include/consts.vh b/rtl/include/consts.vh
index 75ee0bf..75ee0bf 100644
--- a/include/consts.vh
+++ b/rtl/include/consts.vh
diff --git a/include/log2.vh b/rtl/include/log2.vh
index 097061d..097061d 100644
--- a/include/log2.vh
+++ b/rtl/include/log2.vh
diff --git a/src/alu.v b/rtl/src/alu.v
index 8a265ee..8a265ee 100644
--- a/src/alu.v
+++ b/rtl/src/alu.v
diff --git a/src/alu_a_src_mux.v b/rtl/src/alu_a_src_mux.v
index fef701b..fef701b 100644
--- a/src/alu_a_src_mux.v
+++ b/rtl/src/alu_a_src_mux.v
diff --git a/src/alu_b_src_mux.v b/rtl/src/alu_b_src_mux.v
index 5932f9e..5932f9e 100644
--- a/src/alu_b_src_mux.v
+++ b/rtl/src/alu_b_src_mux.v
diff --git a/src/alu_op_decode.v b/rtl/src/alu_op_decode.v
index 4523255..4523255 100644
--- a/src/alu_op_decode.v
+++ b/rtl/src/alu_op_decode.v
diff --git a/src/alu_result_reg.v b/rtl/src/alu_result_reg.v
index cece9e4..cece9e4 100644
--- a/src/alu_result_reg.v
+++ b/rtl/src/alu_result_reg.v
diff --git a/src/arithmetic_unit.v b/rtl/src/arithmetic_unit.v
index 1a2282b..1a2282b 100644
--- a/src/arithmetic_unit.v
+++ b/rtl/src/arithmetic_unit.v
diff --git a/src/clock_divider.v b/rtl/src/clock_divider.v
index a63e943..a63e943 100644
--- a/src/clock_divider.v
+++ b/rtl/src/clock_divider.v
diff --git a/src/control_unit.v b/rtl/src/control_unit.v
index 28f37d9..28f37d9 100644
--- a/src/control_unit.v
+++ b/rtl/src/control_unit.v
diff --git a/src/cpu.v b/rtl/src/cpu.v
index a3b94ff..a3b94ff 100644
--- a/src/cpu.v
+++ b/rtl/src/cpu.v
diff --git a/src/data_reg.v b/rtl/src/data_reg.v
index 473d50a..473d50a 100644
--- a/src/data_reg.v
+++ b/rtl/src/data_reg.v
diff --git a/src/immediate_extend.v b/rtl/src/immediate_extend.v
index 14a9a33..14a9a33 100644
--- a/src/immediate_extend.v
+++ b/rtl/src/immediate_extend.v
diff --git a/src/instruction_reg.v b/rtl/src/instruction_reg.v
index d98ab6d..d98ab6d 100644
--- a/src/instruction_reg.v
+++ b/rtl/src/instruction_reg.v
diff --git a/src/io.v b/rtl/src/io.v
index f53062b..f53062b 100644
--- a/src/io.v
+++ b/rtl/src/io.v
diff --git a/src/logic_unit.v b/rtl/src/logic_unit.v
index 8d8b31d..8d8b31d 100644
--- a/src/logic_unit.v
+++ b/rtl/src/logic_unit.v
diff --git a/src/mem_addr_src_mux.v b/rtl/src/mem_addr_src_mux.v
index 1f34fe1..1f34fe1 100644
--- a/src/mem_addr_src_mux.v
+++ b/rtl/src/mem_addr_src_mux.v
diff --git a/src/memory_interface.v b/rtl/src/memory_interface.v
index 0bc547b..09f05cb 100644
--- a/src/memory_interface.v
+++ b/rtl/src/memory_interface.v
@@ -28,7 +28,7 @@ ram #(.N(32), .SIZE(1024)) ram(
   .data_write(wd)
 );
 
-rom #(.N(32), .SIZE(1024)) rom(
+rom #(.N(32), .SIZE(1024), .ROM_FILE("../../build/rom.hex")) rom(
   .clk(clk),
   .addr(rel_addr),
   .data_read(rom_rd)
diff --git a/src/pc_reg.v b/rtl/src/pc_reg.v
index 11fe9ba..d8dfbec 100644
--- a/src/pc_reg.v
+++ b/rtl/src/pc_reg.v
@@ -11,7 +11,7 @@ module pc_reg (
 `include "include/consts.vh"
 
 always @ (posedge clk or negedge rstn) begin
-  if (!rstn) pc <= PC_INITIAL;
+  if (!rstn)   pc <= PC_INITIAL;
   else if (we) pc <= pc_in;
 end
 
diff --git a/src/ram.v b/rtl/src/ram.v
index 541096e..541096e 100644
--- a/src/ram.v
+++ b/rtl/src/ram.v
diff --git a/src/register_file.v b/rtl/src/register_file.v
index dda44e8..dda44e8 100644
--- a/src/register_file.v
+++ b/rtl/src/register_file.v
diff --git a/src/register_file_reg.v b/rtl/src/register_file_reg.v
index b1bd4fc..b1bd4fc 100644
--- a/src/register_file_reg.v
+++ b/rtl/src/register_file_reg.v
diff --git a/rtl/src/reset_synchronizer.v b/rtl/src/reset_synchronizer.v
new file mode 100644
index 0000000..dc7a80a
--- /dev/null
+++ b/rtl/src/reset_synchronizer.v
@@ -0,0 +1,16 @@
+module reset_synchronizer (
+    input clk,
+    input rstn_async,
+    output rstn
+);
+
+reg [1:0] rstn_sync;
+
+always @(posedge clk or negedge rstn_async) begin
+  if (!rstn_async) rstn_sync <= 2'b00;
+  else             rstn_sync <= {rstn_sync[0], 1'b1};
+end
+
+assign rstn = rstn_sync[1];
+
+endmodule
+\ No newline at end of file
diff --git a/src/result_mux.v b/rtl/src/result_mux.v
index 3c94617..3c94617 100644
--- a/src/result_mux.v
+++ b/rtl/src/result_mux.v
diff --git a/src/rom.v b/rtl/src/rom.v
index d93ef07..29de1da 100644
--- a/src/rom.v
+++ b/rtl/src/rom.v
@@ -1,6 +1,7 @@
 module rom #(
   parameter N = 32, 
-  parameter SIZE = 1024
+  parameter SIZE = 1024,
+  parameter ROM_FILE = "../../build/rom.hex"
 )(
     input clk,
     input [N-1:0] addr,
@@ -14,7 +15,7 @@ module rom #(
 reg [N-1:0] mem [0:SIZE-1];
 
 initial begin
-  $readmemh("build/rom.hex", mem, 0, SIZE-1);
+  $readmemh(ROM_FILE, mem, 0, SIZE-1);
 end
 
 always @(negedge clk) begin
diff --git a/src/shift_unit.v b/rtl/src/shift_unit.v
index ea83e4a..ea83e4a 100644
--- a/src/shift_unit.v
+++ b/rtl/src/shift_unit.v
diff --git a/src/top.v b/rtl/src/top.v
index b10fbca..b10fbca 100644
--- a/src/top.v
+++ b/rtl/src/top.v
diff --git a/sim/gentestvec/Makefile b/sim/gentestvec/Makefile
new file mode 100644
index 0000000..a546b0d
--- /dev/null
+++ b/sim/gentestvec/Makefile
@@ -0,0 +1,33 @@
+BUILD_DIR ?= build
+
+# tools
+CC = clang
+
+# flags
+CFLAGS = -O3
+
+# dirs and files
+SOURCE_DIR = src
+SOURCES = $(wildcard $(SOURCE_DIR)/*.c)
+GENTESTVECS = $(patsubst $(SOURCE_DIR)/%.c, $(BUILD_DIR)/gentestvec_%, $(SOURCES))
+TESTVECS = $(patsubst $(BUILD_DIR)/gentestvec_%, $(BUILD_DIR)/testvec_%.txt, $(GENTESTVECS))
+
+
+# targets
+all: $(TESTVECS)
+
+# build testvec generator executables
+$(BUILD_DIR)/gentestvec_%: $(SOURCE_DIR)/%.c | $(BUILD_DIR)
+	$(CC) $(CFLAGS) -o $@ $<
+
+# generate testvecs
+$(BUILD_DIR)/testvec_%.txt: $(BUILD_DIR)/gentestvec_%
+	$< > $@
+
+$(BUILD_DIR):
+	mkdir -p $(BUILD_DIR)
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+.PHONY: all clean
+\ No newline at end of file
diff --git a/gentestvec/gentestvec_alu.c b/sim/gentestvec/src/alu.c
index 4a11a74..4a11a74 100644
--- a/gentestvec/gentestvec_alu.c
+++ b/sim/gentestvec/src/alu.c
diff --git a/gentestvec/gentestvec_cpu.c b/sim/gentestvec/src/cpu.c
index 8500dd9..8500dd9 100644
--- a/gentestvec/gentestvec_cpu.c
+++ b/sim/gentestvec/src/cpu.c
diff --git a/gentestvec/gentestvec_register_file.c b/sim/gentestvec/src/register_file.c
index 5a50d9b..5a50d9b 100644
--- a/gentestvec/gentestvec_register_file.c
+++ b/sim/gentestvec/src/register_file.c
diff --git a/sim/testbenches/Makefile b/sim/testbenches/Makefile
new file mode 100644
index 0000000..67c8f92
--- /dev/null
+++ b/sim/testbenches/Makefile
@@ -0,0 +1,42 @@
+BUILD_DIR   ?= build
+RTL_SOURCES ?= $(wildcard ../../rtl/src/*.v)
+TESTVEC_DIR ?= ../../build
+INCLUDE     = ../../rtl
+
+TESTVECS ?= $(wildcard $(TESTVEC_DIR)/testvec_*.txt)
+
+# tools
+IVERILOG = iverilog
+VVP      = vvp
+GTKWAVE  = gtkwave
+
+# dirs and files
+SOURCE_DIR = src
+SOURCES = $(wildcard $(SOURCE_DIR)/*.v)
+WAVEFORMS = $(patsubst testvec_%, $(BUILD_DIR)/waveform_%.vcd, $(basename $(notdir $(TESTVECS))))
+
+
+# targets
+all: $(WAVEFORMS)
+
+# generate testbenches
+$(BUILD_DIR)/testbench_%: $(SOURCE_DIR)/testbench_%.v $(RTL_SOURCES) | $(BUILD_DIR) always
+	$(IVERILOG) -I $(INCLUDE) -o $@ $^
+
+# run testbenches
+$(BUILD_DIR)/waveform_%.vcd: $(BUILD_DIR)/testbench_% always
+	$(VVP) $< +testvec=$(shell realpath $(TESTVEC_DIR)/testvec_$*.txt) +waveform=$@
+
+$(BUILD_DIR):
+	mkdir -p $(BUILD_DIR)
+
+wave: all
+	$(GTKWAVE) -a ../../debug/cpu.gtkw $(BUILD_DIR)/waveform_cpu.vcd > /dev/null 2>&1 & disown
+
+# dummy target, s.t. other targets will always be run
+always:
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+.PHONY: all clean always
+\ No newline at end of file
diff --git a/sim/testbench_alu.v b/sim/testbenches/src/testbench_alu.v
index f011ed2..f011ed2 100644
--- a/sim/testbench_alu.v
+++ b/sim/testbenches/src/testbench_alu.v
diff --git a/sim/testbench_cpu.v b/sim/testbenches/src/testbench_cpu.v
index ba40dc2..ba40dc2 100644
--- a/sim/testbench_cpu.v
+++ b/sim/testbenches/src/testbench_cpu.v
diff --git a/sim/testbench_register_file.v b/sim/testbenches/src/testbench_register_file.v
index c1ca542..c1ca542 100644
--- a/sim/testbench_register_file.v
+++ b/sim/testbenches/src/testbench_register_file.v
diff --git a/src/reset_synchronizer.v b/src/reset_synchronizer.v
deleted file mode 100644
index b957a4b..0000000
--- a/src/reset_synchronizer.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module reset_synchronizer (
-    input clk,
-    input rstn_async,
-    output rstn
-);
-
-reg rstn_meta;
-reg rstn_sync_reg;
-
-always @(posedge clk or negedge rstn_async) begin
-  if (!rstn_async) begin
-    rstn_meta <= 1'b0;
-    rstn_sync_reg <= 1'b0;
-  end else begin
-    rstn_meta <= 1'b1;
-    rstn_sync_reg <= rstn_meta;
-  end
-end
-
-assign rstn = rstn_sync_reg;
-
-endmodule
-\ No newline at end of file