refactoring, runs now on fpga

28 files changed, 162 insertions, 171 deletions

diff --git a/debug/cpu.gtkw b/debug/cpu.gtkw
index e611f38..919a1b1 100644
--- a/debug/cpu.gtkw
+++ b/debug/cpu.gtkw
@@ -1,14 +1,14 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Sun May 12 19:27:12 2024
+[*] Mon May 13 05:19:11 2024
 [*]
 [dumpfile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/build/waveform_cpu.vcd"
-[dumpfile_mtime] "Sun May 12 19:21:04 2024"
-[dumpfile_size] 75506
+[dumpfile_mtime] "Mon May 13 05:16:41 2024"
+[dumpfile_size] 75516
 [savefile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/debug/cpu.gtkw"
-[timestart] 277300
+[timestart] 3600
 [size] 1512 916
-[pos] -1 0
+[pos] 0 0
 *-15.000000 27100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] testbench_register_file.
 [treeopen] testbench_register_file.cpu.
diff --git a/prog/src/prog.s b/prog/src/prog.s
index 8f23632..128af52 100644
--- a/prog/src/prog.s
+++ b/prog/src/prog.s
@@ -2,10 +2,15 @@
 .globl _start
 
 _start:
-  
-  addi t0, zero, 3
-  addi t1, zero, 5
-  add  t2, t0, t1
+
+
+  addi t0, zero, 31
+reset_loop:
+  addi t6, zero, 0
+loop:
+  addi t6, t6, 1
+  beq t6, t0, reset_loop
+  j loop
 
 
 halt_loop:
diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v
index d6c3975..87b34d2 100644
--- a/sim/testbench_cpu.v
+++ b/sim/testbench_cpu.v
@@ -7,7 +7,8 @@ reg rst;
 
 cpu cpu (
   .clk(clk),
-  .rstn(!rst)
+  .rstn(!rst),
+  .dbg_t6(_)
 );
 
 integer file, r, eof;
@@ -55,7 +56,7 @@ initial begin
   while (1) begin
     @(posedge clk);
     clk_cycle_count = clk_cycle_count + 1;
-    if (clk_cycle_count == 100) $finish;
+    if (clk_cycle_count == 1000) $finish;
   end
 end
 
diff --git a/src/alu.v b/src/alu.v
index 6962129..b7c5b07 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -1,6 +1,9 @@
 module alu (
-  input [31:0] a, b,
+  input [31:0] a, 
+  input [31:0] b,
+
   input [3:0] op,
+  
   output reg [31:0] result,
   output zero
 );
diff --git a/src/alu_a_src_mux.v b/src/alu_a_src_mux.v
index 0518e0a..b51dd5b 100644
--- a/src/alu_a_src_mux.v
+++ b/src/alu_a_src_mux.v
@@ -1,6 +1,10 @@
 module alu_a_src_mux (
-  input [31:0] src_pc, src_pc_buf, src_rd1_buf,
+  input [31:0] src_pc, 
+  input [31:0] src_pc_buf, 
+  input [31:0] src_rd1_buf,
+
   input [1:0] alu_a_src,
+
   output reg [31:0] alu_a
 );
 
diff --git a/src/alu_b_src_mux.v b/src/alu_b_src_mux.v
index e7df223..99dffab 100644
--- a/src/alu_b_src_mux.v
+++ b/src/alu_b_src_mux.v
@@ -1,6 +1,9 @@
 module alu_b_src_mux (
-  input [31:0] src_rd2_buf, src_imm,
+  input [31:0] src_rd2_buf,
+  input [31:0] src_imm,
+
   input [1:0] alu_b_src,
+  
   output reg [31:0] alu_b
 );
 
diff --git a/src/alu_op_decode.v b/src/alu_op_decode.v
index 5eefcd8..4a812ab 100644
--- a/src/alu_op_decode.v
+++ b/src/alu_op_decode.v
@@ -1,8 +1,10 @@
 module alu_op_decode (
   input [6:0] opcode,
-  input alu_ctrl,
   input [2:0] funct3,
   input [6:0] funct7,
+  
+  input alu_ctrl,
+  
   output reg [3:0] alu_op
 );
 
@@ -23,27 +25,27 @@ always @ (*) begin
   else case (opcode)
     7'b0110011: begin // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
       case (funct3)
-        3'b000: alu_op <= funct7[5] ? ALU_OP_SUB : ALU_OP_ADD;
-        3'b001: alu_op <= ALU_OP_SLL;
-        3'b010: alu_op <= ALU_OP_SLT;
-        3'b011: alu_op <= ALU_OP_SLTU;
-        3'b100: alu_op <= ALU_OP_XOR;
-        3'b101: alu_op <= funct7[5] ? ALU_OP_SRA : ALU_OP_SRL;
-        3'b110: alu_op <= ALU_OP_OR;
-        3'b111: alu_op <= ALU_OP_AND;
+        3'b000:  alu_op <= funct7[5] ? ALU_OP_SUB : ALU_OP_ADD;
+        3'b001:  alu_op <= ALU_OP_SLL;
+        3'b010:  alu_op <= ALU_OP_SLT;
+        3'b011:  alu_op <= ALU_OP_SLTU;
+        3'b100:  alu_op <= ALU_OP_XOR;
+        3'b101:  alu_op <= funct7[5] ? ALU_OP_SRA : ALU_OP_SRL;
+        3'b110:  alu_op <= ALU_OP_OR;
+        3'b111:  alu_op <= ALU_OP_AND;
         default: alu_op <= ALU_OP_ADD;
       endcase
     end
     7'b0010011: begin // ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
       case (funct3)
-        3'b000: alu_op <= ALU_OP_ADD;
-        3'b001: alu_op <= ALU_OP_SLL;
-        3'b010: alu_op <= ALU_OP_SLT;
-        3'b011: alu_op <= ALU_OP_SLTU;
-        3'b100: alu_op <= ALU_OP_XOR;
-        3'b101: alu_op <= funct7[5] ? ALU_OP_SRA : ALU_OP_SRL;
-        3'b110: alu_op <= ALU_OP_OR;
-        3'b111: alu_op <= ALU_OP_AND;
+        3'b000:  alu_op <= ALU_OP_ADD;
+        3'b001:  alu_op <= ALU_OP_SLL;
+        3'b010:  alu_op <= ALU_OP_SLT;
+        3'b011:  alu_op <= ALU_OP_SLTU;
+        3'b100:  alu_op <= ALU_OP_XOR;
+        3'b101:  alu_op <= funct7[5] ? ALU_OP_SRA : ALU_OP_SRL;
+        3'b110:  alu_op <= ALU_OP_OR;
+        3'b111:  alu_op <= ALU_OP_AND;
         default: alu_op <= ALU_OP_ADD;
       endcase
     end
diff --git a/src/alu_result_reg.v b/src/alu_result_reg.v
index b915bdb..8de7a08 100644
--- a/src/alu_result_reg.v
+++ b/src/alu_result_reg.v
@@ -1,5 +1,7 @@
 module alu_result_reg (
-  input clk, rstn,
+  input clk, 
+  input rstn,
+  
   input [31:0] alu_result_in,
   output reg [31:0] alu_result_buf
 );
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v
index 7902e8c..261b526 100644
--- a/src/arithmetic_unit.v
+++ b/src/arithmetic_unit.v
@@ -1,6 +1,9 @@
 module arithmetic_unit (
-  input [31:0] a, b,
+  input [31:0] a, 
+  input [31:0] b,
+
   input [1:0] op,
+  
   output reg [31:0] result
 );
 
diff --git a/src/clock_divider.v b/src/clock_divider.v
index 499d8b2..0ece86d 100644
--- a/src/clock_divider.v
+++ b/src/clock_divider.v
@@ -1,27 +1,29 @@
 module clock_divider #( 
-    parameter N = 2
+  parameter N = 2
 )(
-    input clk,
-    input reset,
-    output reg clk_out
+  input clk,
+  input rstn,
+
+  output reg clk_div
 );
 
-    reg [31:0] counter = 0;
+reg [31:0] counter = 0;
 
-    always @(posedge clk or posedge reset) begin
-        if (reset) begin
-            counter <= 0;
-            clk_out <= 0;
-        end else begin
-            if (counter == (N-1)/2) begin
-                clk_out <= ~clk_out;
-                counter <= counter + 1;
-            end else if (counter >= (N-1)) begin
-                clk_out <= ~clk_out;
-                counter <= 0;
-            end else begin
-                counter <= counter + 1;
-            end
-        end
+always @(posedge clk) begin
+  if (!rstn) begin
+    counter <= 0;
+    clk_div <= 0;
+  end else begin
+    if (counter == (N-1)/2) begin
+      clk_div <= ~clk_div;
+      counter <= counter + 1;
+    end else if (counter >= (N-1)) begin
+      clk_div <= ~clk_div;
+      counter <= 0;
+    end else begin
+      counter <= counter + 1;
     end
+  end
+end
+
 endmodule
diff --git a/src/control_unit.v b/src/control_unit.v
index f6d99ec..9431c25 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -1,18 +1,25 @@
 module control_unit (
  input clk, 
  input rstn,
+
  input [31:0] instr,
  input alu_zero,
+
  output reg [2:0] imm_src,
  output pc_we,
+
  output reg mem_addr_src,
  output reg mem_we,
+
  output reg instr_we,
- output reg [1:0] result_src,
- output [3:0] alu_op,
+
+ output reg rf_we,
+
  output reg [1:0] alu_a_src,
  output reg [1:0] alu_b_src,
- output reg rf_we
+ output [3:0] alu_op,
+
+ output reg [1:0] result_src
 );
 
 parameter s00_fetch     = 4'h0,
@@ -268,7 +275,7 @@ always @ (*) begin
   endcase
 end
 
-alu_op_decode aod (
+alu_op_decode alu_op_decode (
   .opcode(opcode),
   .alu_ctrl(alu_ctrl),
   .funct3(funct3),
diff --git a/src/cpu.v b/src/cpu.v
index b1c28a1..bab556b 100644
--- a/src/cpu.v
+++ b/src/cpu.v
@@ -1,6 +1,7 @@
 module cpu (
   input clk,
-  input rstn
+  input rstn,
+  output [31:0] dbg_t6
 );
 
 
@@ -23,43 +24,34 @@ control_unit control_unit (
 
 
 wire [31:0] pc, pc_buf;
+wire pc_we;
 
 wire [31:0] mem_addr;
-
 wire mem_addr_src;
-
 wire [31:0] mem_rd;
-
 wire mem_we;
-wire instr_we;
 
+wire instr_we;
 wire [31:0] instr;
 
+wire [31:0] imm;
+wire [2:0] imm_src;
+
 wire [31:0] data_buf;
-wire pc_we;
 
 wire rf_we;
-
 wire [31:0] rd1, rd2;
 wire [31:0] rd1_buf, rd2_buf;
 
 wire [31:0] alu_a, alu_b;
-
-wire [31:0] imm;
-wire [2:0] imm_src;
-
 wire [1:0] alu_a_src;
 wire [1:0] alu_b_src;
-
 wire [3:0] alu_op;
-
 wire [31:0] alu_result;
 wire alu_zero;
-
 wire [31:0] alu_result_buf;
 
 wire [1:0] result_src;
-
 wire [31:0] result;
 
 
@@ -119,7 +111,8 @@ register_file register_file (
   .wa3(instr[11:7]),
   .rd1(rd1),
   .rd2(rd2),
-  .wd3(result)
+  .wd3(result),
+  .dbg_t6(dbg_t6)
 );
 
 register_file_reg register_file_reg (
@@ -169,5 +162,4 @@ result_mux result_mux (
   .result(result)
 );
 
-
 endmodule
diff --git a/src/data_reg.v b/src/data_reg.v
index f7530e2..a32a9cf 100644
--- a/src/data_reg.v
+++ b/src/data_reg.v
@@ -1,6 +1,7 @@
 module data_reg (
   input clk,
   input rstn,
+  
   input [31:0] data_in,
   output reg [31:0] data_buf
 );
diff --git a/src/immediate_extend.v b/src/immediate_extend.v
index 749cf2b..404c43d 100644
--- a/src/immediate_extend.v
+++ b/src/immediate_extend.v
@@ -1,6 +1,7 @@
 module immediate_extend (
   input [31:0] instr,
   input [2:0] imm_src,
+  
   output reg [31:0] imm
 );
 
diff --git a/src/instruction_decode.v b/src/instruction_decode.v
deleted file mode 100644
index 2a7eba7..0000000
--- a/src/instruction_decode.v
+++ /dev/null
@@ -1,56 +0,0 @@
-module instruction_decode(
-  input [31:0] instruction,
-  output [6:0] opcode,
-  output [2:0] funct3,
-  output [6:0] funct7,
-  output reg [31:0] immediate,
-  output [4:0] rs1, rs2, rd
-);
-
-parameter INSTRUCTION_FORMAT_UNKNOWN  = 3'b000,
-          INSTRUCTION_FORMAT_R        = 3'b001,
-          INSTRUCTION_FORMAT_I        = 3'b010,
-          INSTRUCTION_FORMAT_S        = 3'b011,
-          INSTRUCTION_FORMAT_B        = 3'b100,
-          INSTRUCTION_FORMAT_U        = 3'b101,
-          INSTRUCTION_FORMAT_J        = 3'b110;
-
-reg [2:0] instruction_format;
-
-always @ (*) begin
-  case (opcode)
-    7'b0110011: instruction_format <= INSTRUCTION_FORMAT_R; // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
-    7'b0010011: instruction_format <= INSTRUCTION_FORMAT_I; // ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
-    7'b0000011: instruction_format <= INSTRUCTION_FORMAT_I; // LB, LH, LW, LBU, LHU
-    7'b1100111: instruction_format <= INSTRUCTION_FORMAT_I; // JALR
-    7'b0100011: instruction_format <= INSTRUCTION_FORMAT_S; // SB, SH, SW
-    7'b1100011: instruction_format <= INSTRUCTION_FORMAT_B; // BEQ, BNE, BLT, BGE, BLTU, BGEU
-    7'b0110111: instruction_format <= INSTRUCTION_FORMAT_U; // LUI
-    7'b0010111: instruction_format <= INSTRUCTION_FORMAT_U; // AUIPC
-    7'b1101111: instruction_format <= INSTRUCTION_FORMAT_J; // JAL
-    7'b0001111: instruction_format <= INSTRUCTION_FORMAT_I; // FENCE, FENCE.I
-    7'b1110011: instruction_format <= INSTRUCTION_FORMAT_I; // ECALL, EBREAK, CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI
-    default:    instruction_format <= INSTRUCTION_FORMAT_UNKNOWN;
-  endcase
-end
-
-always @ (*) begin
-  case (instruction_format)
-    INSTRUCTION_FORMAT_I: immediate <= { {21{instruction[31]}}, instruction[30:20] };
-    INSTRUCTION_FORMAT_S: immediate <= { {21{instruction[31]}}, instruction[30:25], instruction[11:8], instruction[7] };
-    INSTRUCTION_FORMAT_B: immediate <= { {20{instruction[31]}}, instruction[7], instruction[30:25], instruction[11:8], 1'b0 };
-    INSTRUCTION_FORMAT_U: immediate <= { instruction[31], instruction[30:12], 12'b0 };
-    INSTRUCTION_FORMAT_J: immediate <= { {12{instruction[31]}}, instruction[19:12], instruction[20], instruction[30:21], 1'b0 };
-    default: immediate <= 32'b0;
-  endcase
-end
-
-assign opcode = instruction[6:0];
-assign funct3 = instruction[14:12];
-assign funct7 = instruction[31:25];
-assign rs1    = instruction[19:15];
-assign rs2    = instruction[24:20];
-assign rd     = instruction[11:7];
-
-
-endmodule
diff --git a/src/instruction_reg.v b/src/instruction_reg.v
index f3f456e..3c81cf6 100644
--- a/src/instruction_reg.v
+++ b/src/instruction_reg.v
@@ -1,5 +1,8 @@
 module instruction_reg (
-  input clk, rstn, we,
+  input clk, 
+  input rstn, 
+  
+  input we,
   input [31:0] pc_in, instr_in,
   output reg [31:0] pc_buf, instr
 );
diff --git a/src/led_unit.v b/src/led_unit.v
deleted file mode 100644
index cfcbbdf..0000000
--- a/src/led_unit.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module led_unit (
-  input clk,
-  input rst,
-  input we,
-  output reg [31:0] data_read,
-  input [31:0] data_write,
-  output [5:0] led_output
-);
-
-assign led_output = ~data_read[5:0];
-
-always @(posedge clk or posedge rst) begin
-  if (rst) data_read <= 32'b0;
-  else if (we) data_read <= data_write;
-  else data_read <= data_read;
-end
-
-endmodule
diff --git a/src/logic_unit.v b/src/logic_unit.v
index f9f62a2..c717f23 100644
--- a/src/logic_unit.v
+++ b/src/logic_unit.v
@@ -1,6 +1,9 @@
 module logic_unit (
-  input [31:0] a, b,
+  input [31:0] a, 
+  input [31:0] b,
+
   input [1:0] op,
+  
   output reg [31:0] result
 );
   
diff --git a/src/mem_addr_src_mux.v b/src/mem_addr_src_mux.v
index a415287..c5c64f0 100644
--- a/src/mem_addr_src_mux.v
+++ b/src/mem_addr_src_mux.v
@@ -1,6 +1,9 @@
 module mem_addr_src_mux (
-  input [31:0] src_pc, src_result,
+  input [31:0] src_pc, 
+  input [31:0] src_result,
+
   input mem_addr_src,
+  
   output reg [31:0] mem_addr
 );
 
diff --git a/src/memory_interface.v b/src/memory_interface.v
index 0b89e39..0ea837a 100644
--- a/src/memory_interface.v
+++ b/src/memory_interface.v
@@ -1,16 +1,18 @@
 module memory_interface (
   input clk,
   input rstn,
+
   input we,
   input [31:0] addr,
-  output reg [31:0] rd,
-  input [31:0] wd
+  input [31:0] wd,
+
+  output reg [31:0] rd
 );
 
 reg ram_we;
 wire [31:0] ram_read_data, rom_read_data;
 
-ram #(.N(32), .SIZE(1024)) ram(
+ram #(.N(32), .SIZE(16)) ram(
   .clk(clk),
   .rst(!rstn),
   .we(ram_we),
@@ -19,7 +21,7 @@ ram #(.N(32), .SIZE(1024)) ram(
   .data_write(wd)
 );
 
-rom #(.N(32), .SIZE(1024)) rom(
+rom #(.N(32), .SIZE(32)) rom(
   .clk(clk),
   .addr(addr),
   .data_read(rom_read_data)
diff --git a/src/pc_reg.v b/src/pc_reg.v
index 9d7600b..91bf85f 100644
--- a/src/pc_reg.v
+++ b/src/pc_reg.v
@@ -1,15 +1,15 @@
 module pc_reg (
   input clk, 
   input rstn,
+
   input we,
   input [31:0] pc_in,
+
   output reg [31:0] pc
 );
 
-
 parameter PC_INITIAL = 32'h0001_0000;
 
-
 always @ (posedge clk) begin
   if (!rstn) pc <= PC_INITIAL;
   else if (we) pc <= pc_in;
diff --git a/src/ram.v b/src/ram.v
index 1573de8..8234d5d 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -17,7 +17,7 @@ reg [8:0] memory [SIZE-1:0];
 assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
 
 
-always @(posedge clk /*or posedge rst*/) begin
+always @(posedge clk) begin
   if (we) begin
     { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
   end
diff --git a/src/register_file.v b/src/register_file.v
index 9c8f431..12a0433 100644
--- a/src/register_file.v
+++ b/src/register_file.v
@@ -1,8 +1,18 @@
 module register_file (
-  input clk, rstn, we,
-  input [4:0] ra1, ra2, wa3,
+  input clk, 
+  input rstn, 
+  
+  input we,
+  input [4:0] ra1, 
+  input [4:0] ra2, 
+  input [4:0] wa3,
+
   input [31:0] wd3,
-  output [31:0] rd1, rd2
+
+  output [31:0] rd1, 
+  output [31:0] rd2,
+
+  output [31:0] dbg_t6
 );
 
 reg [31:0] regs[31:1];
@@ -74,6 +84,8 @@ assign reg_x29_t4   = regs[29];
 assign reg_x30_t5   = regs[30];
 assign reg_x31_t6   = regs[31];
 
+assign dbg_t6 = reg_x31_t6;
+
 
 assign rd1 = ra1 == 0 ? 32'b0 : regs[ra1];
 assign rd2 = ra2 == 0 ? 32'b0 : regs[ra2];
diff --git a/src/register_file_reg.v b/src/register_file_reg.v
index 0536110..20222d7 100644
--- a/src/register_file_reg.v
+++ b/src/register_file_reg.v
@@ -1,7 +1,12 @@
 module register_file_reg (
-  input clk, rstn,
-  input [31:0] rd1_in, rd2_in,
-  output reg [31:0] rd1_buf, rd2_buf
+  input clk, 
+  input rstn,
+
+  input [31:0] rd1_in, 
+  input [31:0] rd2_in,
+  
+  output reg [31:0] rd1_buf,
+  output reg [31:0] rd2_buf
 );
 
 always @ (posedge clk) begin
diff --git a/src/result_mux.v b/src/result_mux.v
index 9b6cf06..047a392 100644
--- a/src/result_mux.v
+++ b/src/result_mux.v
@@ -1,6 +1,10 @@
 module result_mux (
-  input [31:0] src_alu_result_buf, src_alu_result, src_data_buf,
+  input [31:0] src_alu_result_buf, 
+  input [31:0] src_alu_result, 
+  input [31:0] src_data_buf,
+
   input [1:0] result_src,
+  
   output reg [31:0] result
 );
 
diff --git a/src/rom.v b/src/rom.v
index 8a25f46..381ca64 100644
--- a/src/rom.v
+++ b/src/rom.v
@@ -17,6 +17,4 @@ end
 
 assign data_read = {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
 
-
-
 endmodule
diff --git a/src/shift_unit.v b/src/shift_unit.v
index df4b01d..ae1d665 100644
--- a/src/shift_unit.v
+++ b/src/shift_unit.v
@@ -1,7 +1,9 @@
 module shift_unit (
   input signed [31:0] a,
   input  [4:0] b,
+
   input [1:0] op,
+  
   output reg [31:0] result
 );
 
diff --git a/src/top.v b/src/top.v
index e5a6381..36ce912 100644
--- a/src/top.v
+++ b/src/top.v
@@ -1,20 +1,27 @@
 module top (
 	input clk,
-	input key
+	input key,
+  output [5:0] led
 );
 
 wire rstn, clk_cpu;
 assign rstn = key;
+wire [31:0] dbg_t6;
 
 clock_divider #(.N(1024 * 1024)) clkdiv (
     .clk(clk),
-    .reset(!rstn),
-    .clk_out(clk_cpu)
+    .rstn(rstn),
+    .clk_div(clk_cpu)
 );
 
+assign led[0] = ~clk_cpu;
+assign led[5:1] = ~dbg_t6[4:0];
+
+
 cpu cpu (
   .clk(clk_cpu),
-  .rstn(rstn)
+  .rstn(rstn),
+  .dbg_t6(dbg_t6)
 );
 
 endmodule