control unit

2 files changed, 27 insertions, 8 deletions

diff --git a/src/control_unit.v b/src/control_unit.v
index 35fc32c..5d18f7a 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -3,16 +3,15 @@ module control_unit (
  input [6:0] opcode,
  input [2:0] funct3,
  input [6:0] funct7,
- input zero,
+ input alu_zero,
  output pc_we,
  output mem_addr_src,
  output mem_we,
  output instr_we,
  output [1:0] result_src,
  output [3:0] alu_op,
- output [1:0] alu_src0_src,
- output [1:0] alu_src1_src,
- output [1:0] imm_src,
+ output [1:0] alu_a_src,
+ output [1:0] alu_b_src,
  output rf_we
 );
 
diff --git a/src/cpu.v b/src/cpu.v
index bd282d0..6e72c6b 100644
--- a/src/cpu.v
+++ b/src/cpu.v
@@ -12,10 +12,28 @@ wire instr_we;
 wire rf_we;
 wire alu_zero;
 wire [3:0] alu_op;
-wire [1:0] alu_src_a;
-wire [1:0] alu_src_b;
+wire [1:0] alu_a_src;
+wire [1:0] alu_b_src;
 wire [1:0] result_src;
 
+control_unit cu (
+  .clk(clk),
+  .rst(rst),
+  .opcode(opcode),
+  .funct3(funct3),
+  .funct7(funct7),
+  .alu_zero(alu_zero),
+  .pc_we(pc_we),
+  .mem_addr_src(mem_addr_src),
+  .mem_we(mem_we),
+  .instr_we(instr_we),
+  .result_src(result_src),
+  .alu_op(alu_op),
+  .alu_a_src(alu_a_src),
+  .alu_b_src(alu_b_src),
+  .rf_we(rf_we)
+);
+
 // Fetch
 
 reg [31:0] pc;
@@ -113,7 +131,7 @@ reg [31:0] a, b;
 wire [31:0] alu_result;
 
 always @ (*) begin
-  case(alu_src_a)
+  case(alu_a_src)
     2'b00: a <= pc;
     2'b01: a <= pc_buf;
     2'b10: a <= a_buf;
@@ -122,7 +140,7 @@ always @ (*) begin
 end
 
 always @ (*) begin
-  case(alu_src_b)
+  case(alu_b_src)
     2'b00: b <= b_buf;
     2'b01: b <= immediate;
     2'b10: b <= 32'h4;
@@ -145,6 +163,8 @@ always @ (posedge clk or posedge rst) begin
   else result_buf <= alu_result;
 end
 
+// Writeback
+
 reg [31:0] result;
 
 always @ (*) begin