nextpnr himbaechel

10 files changed, 122 insertions, 44 deletions

diff --git a/Makefile b/Makefile
index dd0371b..b364bde 100644
--- a/Makefile
+++ b/Makefile
@@ -31,7 +31,7 @@ VVP = vvp
 GTKWAVE = gtkwave
 
 YOSYS = yosys
-NEXTPNR = nextpnr-gowin
+NEXTPNR = nextpnr-himbaechel
 GOWIN_PACK = gowin_pack
 PROGRAMMER = openFPGALoader
 
@@ -79,7 +79,7 @@ $(BUILD_DIR)/$(PRJ_NAME)_pnr.json: $(BUILD_DIR)/$(PRJ_NAME).json $(CST_FILES)
 	@echo "==================================================="
 	@echo " Routing"
 	@echo "==================================================="
-	$(NEXTPNR) --json $(BUILD_DIR)/$(PRJ_NAME).json --write $(BUILD_DIR)/$(PRJ_NAME)_pnr.json --device $(DEVICE) --family $(FAMILY) --cst $(CST_FILES)
+	$(NEXTPNR) --json $(BUILD_DIR)/$(PRJ_NAME).json --write $(BUILD_DIR)/$(PRJ_NAME)_pnr.json --device $(DEVICE) --vopt family=$(FAMILY) --vopt cst=$(CST_FILES)
 	@echo "==================================================="
 	@echo " Completed Routing"	
 	@echo "==================================================="
diff --git a/debug/cpu.gtkw b/debug/cpu.gtkw
index 92305c4..2b6da52 100644
--- a/debug/cpu.gtkw
+++ b/debug/cpu.gtkw
@@ -1,22 +1,22 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Wed May 15 06:26:49 2024
+[*] Wed May 15 13:30:34 2024
 [*]
 [dumpfile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/build/waveform_cpu.vcd"
-[dumpfile_mtime] "Wed May 15 06:25:06 2024"
-[dumpfile_size] 6805714
+[dumpfile_mtime] "Wed May 15 07:27:23 2024"
+[dumpfile_size] 6990688
 [savefile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/debug/cpu.gtkw"
-[timestart] 36861700
-[size] 1512 945
+[timestart] 2404400
+[size] 760 916
 [pos] -1 -1
-*-15.000000 59800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-15.000000 2445000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] testbench_register_file.
 [treeopen] testbench_register_file.cpu.
 [treeopen] testbench_register_file.cpu.control_unit.
-[sst_width] 253
-[signals_width] 390
-[sst_expanded] 1
-[sst_vpaned_height] 288
+[sst_width] 39
+[signals_width] 202
+[sst_expanded] 0
+[sst_vpaned_height] 278
 @28
 testbench_register_file.clk
 testbench_register_file.rst
@@ -29,7 +29,7 @@ testbench_register_file.clk_cycle_count[31:0]
 testbench_register_file.cpu.control_unit.state[3:0]
 @28
 testbench_register_file.cpu.instr_we
-@22
+@23
 testbench_register_file.cpu.instr[31:0]
 @28
 testbench_register_file.cpu.control_unit.opcode[6:0]
@@ -51,9 +51,7 @@ testbench_register_file.cpu.pc_we
 -
 @22
 testbench_register_file.cpu.mem_addr[31:0]
-@23
 testbench_register_file.cpu.mem_rd[31:0]
-@22
 testbench_register_file.cpu.rd2_buf[31:0]
 @28
 testbench_register_file.cpu.mem_we
diff --git a/include/consts.vh b/include/consts.vh
index 952b0de..be1c647 100644
--- a/include/consts.vh
+++ b/include/consts.vh
@@ -117,4 +117,23 @@ parameter INSTR_WE_DISABLE  = 1'b0;
 parameter PC_UPDATE_ENABLE  = 1'b1;
 parameter PC_UPDATE_DISABLE = 1'b0;
 parameter BRANCH_ENABLE     = 1'b1;
-parameter BRANCH_DISABLE    = 1'b0;
\ No newline at end of file
+parameter BRANCH_DISABLE    = 1'b0;
+
+parameter IO_BEGIN  = 32'h0000_0000;
+parameter IO_END    = 32'h0000_FFFF;
+parameter ROM_BEGIN = 32'h0001_0000;
+parameter ROM_END   = 32'h000F_FFFF;
+parameter RAM_BEGIN = 32'h0010_0000;
+parameter RAM_END   = 32'hFF0F_FFFF;
+
+// 0000 0000 Reserved
+// 0000 FFFF
+//
+// 0001 0000 ROM
+// 000F FFFF
+//
+// 0010 0000 RAM
+// FF0F FFFF
+//
+// FF10 0000 Reserved
+// FFFF FFFF
diff --git a/prog/src/main.c b/prog/src/main.c
index 8bcdfe2..62b802b 100644
--- a/prog/src/main.c
+++ b/prog/src/main.c
@@ -1,8 +1,13 @@
+#include <stdint.h>
 
-extern void test_prog(void);
+volatile uint32_t *io_in  = (volatile uint32_t *)0x00000000;
+volatile uint32_t *io_out = (volatile uint32_t *)0x00000004; 
 
 int main(void) {
-  test_prog();
+  *io_out = 0;
   while (1) {
+    for (int i = 0; i < 32; ++i) {
+      *io_out = i;
+    }
   }
 }
diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v
index f227320..ba40dc2 100644
--- a/sim/testbench_cpu.v
+++ b/sim/testbench_cpu.v
@@ -5,10 +5,14 @@ module testbench_register_file();
 reg clk;
 reg rst;
 
+reg [31:0] io_in;
+wire [31:0] io_out;
+
 cpu cpu (
   .clk(clk),
   .rstn(!rst),
-  .dbg_t6(_)
+  .io_in(io_in),
+  .io_out(io_out)
 );
 
 integer file, r, eof;
diff --git a/src/cpu.v b/src/cpu.v
index e3c3eb5..35bf03a 100644
--- a/src/cpu.v
+++ b/src/cpu.v
@@ -1,7 +1,8 @@
 module cpu (
   input clk,
   input rstn,
-  output [31:0] dbg_t6
+  input [31:0] io_in,
+  output [31:0] io_out
 );
 
 
@@ -80,7 +81,9 @@ memory_interface memory_interface (
   .we(mem_we),
   .addr(mem_addr),
   .rd(mem_rd),
-  .wd(rd2_buf)
+  .wd(rd2_buf),
+  .io_in(io_in),
+  .io_out(io_out)
 );
 
 instruction_reg instruction_reg (
@@ -115,8 +118,7 @@ register_file register_file (
   .wa3(wa3),
   .rd1(rd1),
   .rd2(rd2),
-  .wd3(result),
-  .dbg_t6(dbg_t6)
+  .wd3(result)
 );
 
 register_file_reg register_file_reg (
diff --git a/src/io.v b/src/io.v
new file mode 100644
index 0000000..f062f31
--- /dev/null
+++ b/src/io.v
@@ -0,0 +1,28 @@
+module io (
+  input clk,
+  input rstn,
+
+  input we,
+  input [31:0] addr,
+  input [31:0] wd,
+
+  output reg [31:0] rd,
+
+  input [31:0] io_in,
+  output reg [31:0] io_out
+);
+
+`include "include/consts.vh"
+
+always @ (posedge clk) begin
+  if (!rstn) begin
+    io_out <= 32'b0;
+  end else if (we && addr == 32'h0000_0004) begin
+    io_out <= wd;
+  end
+  if      (addr == 32'h0000_0000) rd <= io_in;
+  else if (addr == 32'h0000_0004) rd <= io_out;
+  else                            rd <= 32'b0;
+end
+
+endmodule
\ No newline at end of file
diff --git a/src/memory_interface.v b/src/memory_interface.v
index e6ff713..0bc547b 100644
--- a/src/memory_interface.v
+++ b/src/memory_interface.v
@@ -6,11 +6,17 @@ module memory_interface (
   input [31:0] addr,
   input [31:0] wd,
 
-  output reg [31:0] rd
+  output reg [31:0] rd,
+
+  input [31:0] io_in,
+  output [31:0] io_out
 );
 
+`include "include/consts.vh"
+
 reg ram_we;
-wire [31:0] ram_read_data, rom_read_data;
+reg io_we;
+wire [31:0] ram_rd, rom_rd;
 reg [31:0] rel_addr;
 
 ram #(.N(32), .SIZE(1024)) ram(
@@ -18,14 +24,25 @@ ram #(.N(32), .SIZE(1024)) ram(
   .rstn(rstn),
   .we(ram_we),
   .addr(rel_addr),
-  .data_read(ram_read_data),
+  .data_read(ram_rd),
   .data_write(wd)
 );
 
 rom #(.N(32), .SIZE(1024)) rom(
   .clk(clk),
   .addr(rel_addr),
-  .data_read(rom_read_data)
+  .data_read(rom_rd)
+);
+
+io io(
+  .clk(clk),
+  .rstn(rstn),
+  .we(io_we),
+  .addr(rel_addr),
+  .rd(io_rd),
+  .wd(wd),
+  .io_in(io_in),
+  .io_out(io_out)
 );
 
 
@@ -42,17 +59,23 @@ rom #(.N(32), .SIZE(1024)) rom(
 // FFFF FFFF
 
 
-always @(*) begin
-  if (         addr >= 32'h0001_0000 && addr <= 32'h000F_0000) begin
-    ram_we = 0;
-    rd = rom_read_data;
-    rel_addr = addr - 32'h0001_0000;
-  end else if (addr >= 32'h0010_0000 && addr <= 32'hFF0F_0000) begin
+always @ (*) begin
+  rd       = 0;
+  rel_addr = 0;
+  ram_we   = 0;
+  io_we    = 0;
+  if (         addr >= ROM_BEGIN && addr <= ROM_END) begin
+    rd = rom_rd;
+    rel_addr = addr - ROM_BEGIN;
+  end else if (addr >= RAM_BEGIN && addr <= RAM_END) begin
     ram_we = we;
-    rd = ram_read_data;
-    rel_addr = addr - 32'h0010_0000;
+    rd = ram_rd;
+    rel_addr = addr - RAM_BEGIN;
+  end else if (addr >= IO_BEGIN && addr <= IO_END) begin
+    io_we = we;
+    rd = io_rd;
+    rel_addr = addr - IO_BEGIN;
   end else begin
-    ram_we = 0;
     rd = 0;
     rel_addr = 0;
   end
diff --git a/src/register_file.v b/src/register_file.v
index 7f83704..dda44e8 100644
--- a/src/register_file.v
+++ b/src/register_file.v
@@ -10,9 +10,7 @@ module register_file (
   input [31:0] wd3,
 
   output [31:0] rd1, 
-  output [31:0] rd2,
-
-  output [31:0] dbg_t6
+  output [31:0] rd2
 );
 
 reg [31:0] regs[31:1];
@@ -84,8 +82,6 @@ assign reg_x29_t4   = regs[29];
 assign reg_x30_t5   = regs[30];
 assign reg_x31_t6   = regs[31];
 
-assign dbg_t6 = reg_x31_t6;
-
 
 assign rd1 = ra1 == 0 ? 32'b0 : regs[ra1];
 assign rd2 = ra2 == 0 ? 32'b0 : regs[ra2];
diff --git a/src/top.v b/src/top.v
index 36ce912..86f26ce 100644
--- a/src/top.v
+++ b/src/top.v
@@ -6,7 +6,9 @@ module top (
 
 wire rstn, clk_cpu;
 assign rstn = key;
-wire [31:0] dbg_t6;
+
+wire [31:0] io_in;
+wire [31:0] io_out;
 
 clock_divider #(.N(1024 * 1024)) clkdiv (
     .clk(clk),
@@ -15,13 +17,14 @@ clock_divider #(.N(1024 * 1024)) clkdiv (
 );
 
 assign led[0] = ~clk_cpu;
-assign led[5:1] = ~dbg_t6[4:0];
+assign led[5:1] = ~io_out[4:0];
 
 
 cpu cpu (
   .clk(clk_cpu),
   .rstn(rstn),
-  .dbg_t6(dbg_t6)
+  .io_in(io_in),
+  .io_out(io_out)
 );
 
 endmodule