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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-08 12:14:49 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-08 12:14:49 +0200
commit4895d68fb533dc599b752936ef1dc8f5af80bc5a (patch)
tree4b649a4d8c7217f5d7d5ce4684b1d72a2c18c16d
parent7ff0d605067d57f638da50e53eb4a7dbb7ef11e6 (diff)
downloadriscv_cpu-4895d68fb533dc599b752936ef1dc8f5af80bc5a.tar.gz
riscv_cpu-4895d68fb533dc599b752936ef1dc8f5af80bc5a.zip
updated readme for make rom
-rw-r--r--README.md3
-rwxr-xr-xprog/build.sh6
2 files changed, 2 insertions, 7 deletions
diff --git a/README.md b/README.md
index 4a25172..79ddbeb 100644
--- a/README.md
+++ b/README.md
@@ -11,8 +11,9 @@ The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardw
* `make all` alias for `make simulate`.
* `make simulate` to run all the testbenches (sim/testbench_*.v).
* `make bitstream` to synthesize, place and route the design and to generate the bitstream.
-* `make program` to upload the bitstream to the FPGA.
+* `make upload` to upload the bitstream to the FPGA.
* `make flash` to flash the bitsream to the FPGA.
* `make clean` to clean build files.
* `gtkwave build/waveform_*.vcd` to view waveform of corresponding testbench.
+* `make rom` to compile source files in prog/src, link and generate rom file.
diff --git a/prog/build.sh b/prog/build.sh
deleted file mode 100755
index 22557b4..0000000
--- a/prog/build.sh
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-riscv64-unknown-elf-as -march=rv32i -mabi=ilp32 -o main.o main.s
-riscv64-unknown-elf-ld -T link.ld -m elf32lriscv -o main.elf main.o
-riscv64-unknown-elf-objcopy -O binary main.elf main.bin
-xxd -g 1 -c 1 -p main.bin >main.hex
-cp -f main.hex ../rom/rom.hex