renamed some signals

6 files changed, 57 insertions, 52 deletions

diff --git a/README.md b/README.md
index 1f33d03..34e6d4e 100644
--- a/README.md
+++ b/README.md
@@ -2,6 +2,10 @@
 
 An attempt at building a simple RISCV CPU in verilog.
 
+## FPGA
+
+The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html) with a GW1NR-LV9QN88PC6/I5 FPGA. There is a crystal clock onboard running at 27 MHz.
+
 ## Build
 
 * `make all` alias for `make simulate`.
@@ -10,3 +14,4 @@ An attempt at building a simple RISCV CPU in verilog.
 * `make program` to upload the bitstream to the FPGA.
 * `make flash` to flash the bitsream to the FPGA.
 * `make clean` to clean build files.
+
diff --git a/sim/testbench_alu.v b/sim/testbench_alu.v
index 7d67d5c..068efc3 100644
--- a/sim/testbench_alu.v
+++ b/sim/testbench_alu.v
@@ -76,11 +76,11 @@ module testbench_alu();
   
 
   alu #(.N(32)) alu (
-    .A(a),
-    .B(b),
-    .OP(op),
-    .RESULT(result),
-    .ZERO(zero)
+    .alu_src0(a),
+    .alu_src1(b),
+    .alu_op(op),
+    .alu_result(result),
+    .alu_zero(zero)
   );
 
 endmodule
diff --git a/src/alu.v b/src/alu.v
index d54721b..2eaf2b0 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -1,43 +1,43 @@
 module alu #(
   parameter N = 32
 )(
-  input [N-1:0] A, B,
-  input [3:0] OP, // OP[3:2] 00: ARITHMETIC, 01: LOGIC, 10: SHIFT 
-  output reg [N-1:0] RESULT,
-  output ZERO
+  input [N-1:0] alu_src0, alu_src1,
+  input [3:0] alu_op, // alu_op[3:2] 00: ARITHMETIC, 01: LOGIC, 10: SHIFT 
+  output reg [N-1:0] alu_result,
+  output alu_zero
 );
 
 wire [N-1:0] arithmetic_result, logic_result, shift_result;
 
 arithmetic_unit #(.N(N)) au (
-  .A(A),
-  .B(B),
-  .OP(OP[1:0]),
-  .RESULT(arithmetic_result)
+  .au_src0(alu_src0),
+  .au_src1(alu_src1),
+  .au_op(alu_op[1:0]),
+  .au_result(arithmetic_result)
 );
 
 logic_unit #(.N(N)) lu (
-  .A(A),
-  .B(B),
-  .OP(OP[1:0]),
-  .RESULT(logic_result)
+  .lu_src0(alu_src0),
+  .lu_src1(alu_src1),
+  .lu_op(alu_op[1:0]),
+  .lu_result(logic_result)
 );
 
 shift_unit #(.N(N)) su (
-  .A(A),
-  .SHAMT(B),
-  .OP(OP[1:0]),
-  .RESULT(shift_result)
+  .su_src0(alu_src0),
+  .su_shamt(alu_src1),
+  .su_op(alu_op[1:0]),
+  .su_result(shift_result)
 );
 
 always @ (*) begin
-  case (OP[3:2])
-    2'b00: RESULT <= arithmetic_result;
-    2'b01: RESULT <= logic_result;
-    2'b10: RESULT <= shift_result;
+  case (alu_op[3:2])
+    2'b00: alu_result <= arithmetic_result;
+    2'b01: alu_result <= logic_result;
+    2'b10: alu_result <= shift_result;
   endcase
 end
 
-assign ZERO = ~|RESULT;
+assign alu_zero = ~|alu_result;
 
 endmodule
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v
index 64ec0f9..71255c2 100644
--- a/src/arithmetic_unit.v
+++ b/src/arithmetic_unit.v
@@ -1,23 +1,23 @@
 module arithmetic_unit #(
   parameter N = 32
 )(
-  input [N-1:0] A, B,
-  input [1:0] OP, // 00: ADD, 01: SUB, 11: SLT
-  output [N-1:0] RESULT
+  input [N-1:0] au_src0, au_src1,
+  input [1:0] au_op, // 00: ADD, 01: SUB, 11: SLT
+  output [N-1:0] au_result
 );
 
-wire [N-1:0] b, sum;
-wire cin, altb, overflow;
+wire [N-1:0] au_src1_inv, au_sum;
+wire au_cin, au_src0_lt_src1, au_overflow;
 
-assign b = OP[0] ? ~B : B;
-assign cin = OP[0];
+assign au_src1_inv = au_op[0] ? ~au_src1 : au_src1;
+assign au_cin = au_op[0];
 
-assign sum = A + b + cin;
+assign au_sum = au_src0 + au_src1_inv + au_cin;
 
-assign overflow = ~(A[N-1] ^ B[N-1] ^ OP[0]) & (A[N-1] ^ sum[N-1]);
+assign au_overflow = ~(au_src0[N-1] ^ au_src1[N-1] ^ au_op[0]) & (au_src0[N-1] ^ au_sum[N-1]);
 
-assign altb = overflow ^ sum[N-1];
+assign au_src0_lt_src1 = au_overflow ^ au_sum[N-1];
 
-assign RESULT = OP[1] ? {{(N-1){1'b0}}, altb} : sum;
+assign au_result = au_op[1] ? {{(N-1){1'b0}}, au_src0_lt_src1} : au_sum;
 
 endmodule
diff --git a/src/logic_unit.v b/src/logic_unit.v
index 5ada9c9..85c9137 100644
--- a/src/logic_unit.v
+++ b/src/logic_unit.v
@@ -1,16 +1,16 @@
 module logic_unit #(
   parameter N = 32
 )(
-  input [N-1:0] A, B,
-  input [1:0] OP, // 00: AND, 01: OR, 10: XOR
-  output reg [N-1:0] RESULT
+  input [N-1:0] lu_src0, lu_src1,
+  input [1:0] lu_op, // 00: AND, 01: OR, 10: XOR
+  output reg [N-1:0] lu_result
 );
   
   always @ (*) begin
-    case (OP)
-      2'b00: RESULT <= A & B;
-      2'b01: RESULT <= A | B;
-      2'b10: RESULT <= A ^ B;
+    case (lu_op)
+      2'b00: lu_result <= lu_src0 & lu_src1;
+      2'b01: lu_result <= lu_src0 | lu_src1;
+      2'b10: lu_result <= lu_src0 ^ lu_src1;
     endcase
   end
 
diff --git a/src/shift_unit.v b/src/shift_unit.v
index 1f2c96b..372fec0 100644
--- a/src/shift_unit.v
+++ b/src/shift_unit.v
@@ -1,17 +1,17 @@
 module shift_unit #(
   parameter N = 32
 )(
-  input signed [N-1:0] A,
-  input  [N-1:0] SHAMT,
-  input [1:0] OP, // 00: SLL, 01: SRL, 11: SRA 
-  output reg [N-1:0] RESULT
+  input signed [N-1:0] su_src0,
+  input  [N-1:0] su_shamt,
+  input [1:0] su_op, // 00: SLL, 01: SRL, 11: SRA 
+  output reg [N-1:0] su_result
 );
 
 always @ (*) begin
-  case (OP)
-    2'b00: RESULT <= A << SHAMT % N;
-    2'b01: RESULT <= A >> SHAMT % N;
-    2'b11: RESULT <= A >>> SHAMT % N;
+  case (su_op)
+    2'b00: su_result <= su_src0 << su_shamt % N;
+    2'b01: su_result <= su_src0 >> su_shamt % N;
+    2'b11: su_result <= su_src0 >>> su_shamt % N;
   endcase
 end