added support for multiple testbenches

5 files changed, 112 insertions, 99 deletions

diff --git a/Makefile b/Makefile
index 3591fb5..e23abd1 100644
--- a/Makefile
+++ b/Makefile
@@ -1,58 +1,81 @@
-PROJ_NAME = riscv_cpu
+PRJ_NAME = riscv_cpu
 TOP_MODULE = top
 
-BUILD_DIR = build
-
+# Directories
 SRC_DIR = src
-CONSTRAINTS_DIR = constraints
 SIM_DIR = sim
-GENTESTS_DIR = tests
+GENTESTVEC_DIR = gentestvec
+CST_DIR = cst
+BUILD_DIR = build
 
-SOURCES = $(wildcard $(SRC_DIR)/*.v)
-TESTBENCH = $(SIM_DIR)/testbench.v
-CONSTRAINTS = $(CONSTRAINTS_DIR)/tangnano9k.cst
+# Source Files
+SRC_FILES = $(wildcard $(SRC_DIR)/*.v)
+SIM_FILES = $(wildcard $(SIM_DIR)/testbench_*.v)
+GENTESTVEC_FILES = $(wildcard $(GENTESTVEC_DIR)/gentestvec_*.c)
+CST_FILES = $(wildcard $(CST_DIR)/*.cst)
 
-GENTESTS_SOURCES = $(wildcard $(GENTESTS_DIR)/*.c)
-GENTESTS_BINARIES = $(patsubst $(GENTESTS_DIR)/%.c,$(BUILD_DIR)/%,$(GENTESTS_SOURCES))
+# Output Files
+SIM_EXECUTABLES = $(patsubst $(SIM_DIR)/testbench_%.v, $(BUILD_DIR)/testbench_%,$(SIM_FILES))
+GENTESTVEC_EXECUTABLES = $(patsubst $(GENTESTVEC_DIR)/gentestvec_%.c, $(BUILD_DIR)/gentestvec_%,$(GENTESTVEC_FILES))
+TESTVECTOR_FILES = $(patsubst $(BUILD_DIR)/gentestvec_%, $(BUILD_DIR)/testvec_%.txt, $(GENTESTVEC_EXECUTABLES))
+WAVEFORM_FILES = $(patsubst $(BUILD_DIR)/testbench_%, $(BUILD_DIR)/waveform_%.vcd, $(SIM_EXECUTABLES))
 
-BITSTREAM = $(BUILD_DIR)/$(PROJ_NAME).fs
+BITSTREAM = $(BUILD_DIR)/$(PRJ_NAME).fs
+
+# Programs
+CC = clang
+CFLAGS = -O3
+
+IVERILOG = iverilog
+VVP = vvp
+GTKWAVE = gtkwave
 
 YOSYS = yosys
 NEXTPNR = nextpnr-gowin
 GOWIN_PACK = gowin_pack
 PROGRAMMER = openFPGALoader
-IVERILOG = iverilog
-VVP = vvp
-GTKWAVE = gtkwave
-CC = clang
 
 FAMILY = GW1N-9C
 DEVICE = GW1NR-LV9QN88PC6/I5
 BOARD = tangnano9k
 
-all: $(BITSTREAM)
+all: simulate
 
-$(BUILD_DIR)/$(PROJ_NAME).json: $(SOURCES)
-	@echo "=================================================="
-	@echo "Synthesizing"
-	@echo "=================================================="
-	
-	@mkdir -p $(BUILD_DIR)
-	$(YOSYS) -p "synth_gowin -top $(TOP_MODULE)" -o $(BUILD_DIR)/$(PROJ_NAME).json $(SOURCES)
-	
-$(BUILD_DIR)/$(PROJ_NAME)_pnr.json: $(BUILD_DIR)/$(PROJ_NAME).json $(CONSTRAINTS)
+
+$(BUILD_DIR)/$(PRJ_NAME).json: $(SRC_FILES) | $(BUILD_DIR)
+	@echo
 	@echo "=================================================="
-	@echo "Routing"
+	@echo " Synthesizing"
 	@echo "=================================================="
-
-	$(NEXTPNR) --json $(BUILD_DIR)/$(PROJ_NAME).json --write $(BUILD_DIR)/$(PROJ_NAME)_pnr.json --device $(DEVICE) --family $(FAMILY) --cst $(CONSTRAINTS)
-
-$(BITSTREAM): $(BUILD_DIR)/$(PROJ_NAME)_pnr.json
+	$(YOSYS) -p "synth_gowin -top $(TOP_MODULE)" -o $(BUILD_DIR)/$(PRJ_NAME).json $(SRC_FILES)
 	@echo "=================================================="
-	@echo "Generating Bitstream"
+	@echo " Completed Synthesis"
 	@echo "=================================================="
-
-	$(GOWIN_PACK) -d $(FAMILY) -o $(BITSTREAM) $(BUILD_DIR)/$(PROJ_NAME)_pnr.json
+	@echo
+
+$(BUILD_DIR)/$(PRJ_NAME)_pnr.json: $(BUILD_DIR)/$(PRJ_NAME).json $(CST_FILES)
+	@echo
+	@echo "==================================================="
+	@echo " Routing"
+	@echo "==================================================="
+	$(NEXTPNR) --json $(BUILD_DIR)/$(PRJ_NAME).json --write $(BUILD_DIR)/$(PRJ_NAME)_pnr.json --device $(DEVICE) --family $(FAMILY) --cst $(CST_FILES)
+	@echo "==================================================="
+	@echo " Completed Routing"	
+	@echo "==================================================="
+	@echo
+
+$(BITSTREAM): $(BUILD_DIR)/$(PRJ_NAME)_pnr.json
+	@echo
+	@echo "==================================================="
+	@echo " Generating Bitstream"
+	@echo "==================================================="
+	$(GOWIN_PACK) -d $(FAMILY) -o $(BITSTREAM) $(BUILD_DIR)/$(PRJ_NAME)_pnr.json
+	@echo "==================================================="
+	@echo " Generated Bitstream"
+	@echo "==================================================="
+	@echo
+
+bitstream: $(BITSTREAM)
 	
 program: $(BITSTREAM)
 	$(PROGRAMMER) -b $(BOARD) $(BITSTREAM)
@@ -60,28 +83,39 @@ program: $(BITSTREAM)
 flash: $(BITSTREAM)
 	$(PROGRAMMER) -b $(BOARD) -f $(BITSTREAM)
 
+simulate: $(WAVEFORM_FILES)
+
+# Build the testbench executables
+$(BUILD_DIR)/testbench_%: $(SIM_DIR)/testbench_%.v $(SRC_FILES) | $(BUILD_DIR)
+	$(IVERILOG) -o $@ $^
+
+# Build the test vector generator executables
+$(BUILD_DIR)/gentestvec_%: $(GENTESTVEC_DIR)/gentestvec_%.c | $(BUILD_DIR)
+	$(CC) $(CFLAGS) -o $@ $<
+
+# Generate the test vector files
+$(BUILD_DIR)/testvec_%.txt: $(BUILD_DIR)/gentestvec_%
+	$< > $@
+
+# Run the simulation and generate the waveform files
+$(BUILD_DIR)/waveform_%.vcd: $(BUILD_DIR)/testbench_% $(BUILD_DIR)/testvec_%.txt
+	@echo
+	@echo "==================================================="
+	@echo " Running Testbench ($*)"
+	@echo "==================================================="
+	$(VVP) $< +testvec=$(BUILD_DIR)/testvec_$*.txt +waveform=$@
+	@echo "==================================================="
+	@echo " Completed Testbench ($*)"
+	@echo "==================================================="
+	@echo
+
+# Create the build directory
+$(BUILD_DIR):
+	mkdir -p $(BUILD_DIR)
+
+# Clean
 clean:
 	rm -rf $(BUILD_DIR)
 
-$(BUILD_DIR)/%: $(GENTESTS_DIR)/%.c
-	@mkdir -p $(BUILD_DIR)
-	$(CC) -o $@ $<
-
-tests: $(GENTESTS_BINARIES)
-	@for bin in $(GENTESTS_BINARIES); do \
-		./$$bin > $$bin.txt; \
-	done
-
-simulate: $(BUILD_DIR)/testbench.vcd
-
-wave: $(BUILD_DIR)/testbench.vcd
-	$(GTKWAVE) $(BUILD_DIR)/testbench.vcd
-
-$(BUILD_DIR)/testbench: $(SOURCES) $(TESTBENCH)	
-	@mkdir -p $(BUILD_DIR)
-	$(IVERILOG) -o $(BUILD_DIR)/testbench $(SOURCES) $(TESTBENCH)
-
-$(BUILD_DIR)/testbench.vcd: $(BUILD_DIR)/testbench tests
-	cd $(BUILD_DIR); $(VVP) testbench
+.PHONY: all simulate bitsream program flash clean
 
-.PHONY: all program flash simulate wave clean tests
diff --git a/constraints/tangnano9k.cst b/cst/tangnano9k.cst
index e909e36..e909e36 100644
--- a/constraints/tangnano9k.cst
+++ b/cst/tangnano9k.cst
diff --git a/tests/alu_testvec.c b/gentestvec/gentestvec_alu.c
index 39de43e..39de43e 100644
--- a/tests/alu_testvec.c
+++ b/gentestvec/gentestvec_alu.c
diff --git a/sim/testbench.v b/sim/testbench_alu.v
index 2d485ea..7d67d5c 100644
--- a/sim/testbench.v
+++ b/sim/testbench_alu.v
@@ -1,12 +1,31 @@
 `timescale 1ns / 1ps
 
-module testbench();
+module testbench_alu();
 
   reg reset = 0;
+
+  reg [1023:0] testvec_filename;
+  reg [1023:0] waveform_filename;
+
+  initial begin
+    if ($value$plusargs("testvec=%s", testvec_filename)) begin
+      $display("Using test vector file: %s", testvec_filename);
+    end else begin
+      $display("Error: no test vector file specified.");
+      $finish;
+    end
+
+    if ($value$plusargs("waveform=%s", waveform_filename)) begin
+      $display("Using waveform file: %s", waveform_filename);
+    end else begin
+      $display("Error: no waveform file specified.");
+      $finish;
+    end
+  end
   
   initial begin
-    $dumpfile("testbench.vcd");
-    $dumpvars(0,testbench);
+    $dumpfile(waveform_filename);
+    $dumpvars(0,testbench_alu);
   end
 
   reg clk = 0;
@@ -25,7 +44,8 @@ module testbench();
   reg [103:0] alu_testvec [0:9999];
 
   initial begin
-    $readmemh("alu_testvec.txt", alu_testvec);
+    #5;
+    $readmemh(testvec_filename, alu_testvec);
     alu_test_count = 0;
     alu_error_count = 0;
   end
diff --git a/src/register_file.v b/src/register_file.v
deleted file mode 100644
index 4f09773..0000000
--- a/src/register_file.v
+++ /dev/null
@@ -1,41 +0,0 @@
-module register_file #(
-  parameter N = 32,
-  parameter XLEN = 32
-)(
-  input [CLOG2(XLEN)-1:0] A1, A2, A3,
-  input CLK,
-  input RST,
-  input WE3,
-  input [N-1:0] WD3,
-  output [N-1:0] RD1, RD2
-);
-
-  reg [N-1:0] registers[XLEN-1:0];
-
-  assign RD1 = A1 == 0 ? 0 : registers[A1];
-  assign RD2 = A2 == 0 ? 0 : registers[A2];
-
-  always @ (posedge CLK or negedge RST) begin
-    if (!RST) begin
-      integer i;
-      for (i = 0; i < XLEN; i = i + 1) begin
-        registers[i] <= 0;
-      end
-    end else if (WE3 && (A3 != 0)) begin
-      registers[A3] <= WD3;
-    end
-  end
-
-
-
-  function integer CLOG2(input integer value);
-    integer i;
-    begin
-      value = value - 1;
-      for (i = 0; value > 0; i = i + 1)
-        value = value >> 1;
-      CLOG2 = i;
-    end
-  endfunction
-
-endmodule