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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 07:28:34 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 07:28:34 +0200
commit9f1ab1f834c58c231617f3be12f16793061d4630 (patch)
treedfb5040d4568010ecc765dee61f1ade9a4d7fc02
parent5a549e61af1df0c4016f00af830120d21a88a0e7 (diff)
downloadriscv_cpu-9f1ab1f834c58c231617f3be12f16793061d4630.tar.gz
riscv_cpu-9f1ab1f834c58c231617f3be12f16793061d4630.zip
cleaned up graphics
-rw-r--r--README.md9
-rw-r--r--include/consts.vh10
-rw-r--r--res/control_unit_fsm.jpgbin998456 -> 1002418 bytes
-rw-r--r--res/memory_layout.jpgbin344615 -> 338831 bytes
-rw-r--r--res/microarchitecure.jpgbin698890 -> 652880 bytes
-rw-r--r--res/waveform_add_two_numbers.pngbin672412 -> 678778 bytes
-rw-r--r--src/alu_a_src_mux.v6
-rw-r--r--src/cpu.v2
-rw-r--r--src/result_mux.v6
9 files changed, 20 insertions, 13 deletions
diff --git a/README.md b/README.md
index 820055f..b79d486 100644
--- a/README.md
+++ b/README.md
@@ -61,12 +61,19 @@ The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardw
* [Example RISCV Cores](https://github.com/yunchenlo/awesome-RISCV-Cores)
## Design
-### Microarchitecture
+
+### Microarchitecture (RISC-V multicycle rv32i without ECALL/EBREAK)
+
![Microarchitecture](res/microarchitecure.jpg)
+
### Control Unit FSM
+
![Control Unit FSM](res/control_unit_fsm.jpg)
+
### Memory Layout
+
![Memory Layout](res/memory_layout.jpg)
+
## Waveform Example
Here we can see the waveforms of various internal signal of the CPU, executing the following instructions:
diff --git a/include/consts.vh b/include/consts.vh
index e0f6e5f..75ee0bf 100644
--- a/include/consts.vh
+++ b/include/consts.vh
@@ -1,16 +1,16 @@
parameter ALU_A_SRC_PC = 3'b000;
parameter ALU_A_SRC_PC_BUF = 3'b001;
-parameter ALU_A_SRC_RD1_BUF = 3'b010;
-parameter ALU_A_SRC_RD1 = 3'b011;
+parameter ALU_A_SRC_RD1 = 3'b010;
+parameter ALU_A_SRC_RD1_BUF = 3'b011;
parameter ALU_A_SRC_0 = 3'b100;
parameter ALU_B_SRC_RD2_BUF = 2'b00;
parameter ALU_B_SRC_IMM = 2'b01;
parameter ALU_B_SRC_4 = 2'b10;
-parameter RESULT_SRC_ALU_RESULT_BUF = 2'b00;
-parameter RESULT_SRC_DATA_BUF = 2'b01;
-parameter RESULT_SRC_ALU_RESULT = 2'b10;
+parameter RESULT_SRC_ALU_RESULT = 2'b00;
+parameter RESULT_SRC_ALU_RESULT_BUF = 2'b01;
+parameter RESULT_SRC_DATA_BUF = 2'b10;
parameter MEM_ADDR_SRC_PC = 1'b0;
parameter MEM_ADDR_SRC_RESULT = 1'b1;
diff --git a/res/control_unit_fsm.jpg b/res/control_unit_fsm.jpg
index a6b2bfc..9b52160 100644
--- a/res/control_unit_fsm.jpg
+++ b/res/control_unit_fsm.jpg
Binary files differ
diff --git a/res/memory_layout.jpg b/res/memory_layout.jpg
index 893aa4d..e23833c 100644
--- a/res/memory_layout.jpg
+++ b/res/memory_layout.jpg
Binary files differ
diff --git a/res/microarchitecure.jpg b/res/microarchitecure.jpg
index f182fe8..95e06d5 100644
--- a/res/microarchitecure.jpg
+++ b/res/microarchitecure.jpg
Binary files differ
diff --git a/res/waveform_add_two_numbers.png b/res/waveform_add_two_numbers.png
index afd7714..d976bc8 100644
--- a/res/waveform_add_two_numbers.png
+++ b/res/waveform_add_two_numbers.png
Binary files differ
diff --git a/src/alu_a_src_mux.v b/src/alu_a_src_mux.v
index 8998b55..fef701b 100644
--- a/src/alu_a_src_mux.v
+++ b/src/alu_a_src_mux.v
@@ -1,8 +1,8 @@
module alu_a_src_mux (
input [31:0] src_pc,
- input [31:0] src_pc_buf,
- input [31:0] src_rd1_buf,
+ input [31:0] src_pc_buf,
input [31:0] src_rd1,
+ input [31:0] src_rd1_buf,
input [2:0] alu_a_src,
@@ -15,8 +15,8 @@ always @(*) begin
case (alu_a_src)
ALU_A_SRC_PC: alu_a = src_pc;
ALU_A_SRC_PC_BUF: alu_a = src_pc_buf;
- ALU_A_SRC_RD1_BUF: alu_a = src_rd1_buf;
ALU_A_SRC_RD1: alu_a = src_rd1;
+ ALU_A_SRC_RD1_BUF: alu_a = src_rd1_buf;
ALU_A_SRC_0: alu_a = 32'b0;
default: alu_a = 32'b0;
endcase
diff --git a/src/cpu.v b/src/cpu.v
index 35bf03a..a3b94ff 100644
--- a/src/cpu.v
+++ b/src/cpu.v
@@ -162,8 +162,8 @@ alu_result_reg alu_result_reg (
);
result_mux result_mux (
- .src_alu_result_buf(alu_result_buf),
.src_alu_result(alu_result),
+ .src_alu_result_buf(alu_result_buf),
.src_data_buf(data_buf),
.result_src(result_src),
.result(result)
diff --git a/src/result_mux.v b/src/result_mux.v
index 9aab115..3c94617 100644
--- a/src/result_mux.v
+++ b/src/result_mux.v
@@ -1,6 +1,6 @@
module result_mux (
- input [31:0] src_alu_result_buf,
- input [31:0] src_alu_result,
+ input [31:0] src_alu_result,
+ input [31:0] src_alu_result_buf,
input [31:0] src_data_buf,
input [1:0] result_src,
@@ -12,8 +12,8 @@ module result_mux (
always @(*) begin
case (result_src)
- RESULT_SRC_ALU_RESULT_BUF: result = src_alu_result_buf;
RESULT_SRC_DATA_BUF: result = src_data_buf;
+ RESULT_SRC_ALU_RESULT_BUF: result = src_alu_result_buf;
RESULT_SRC_ALU_RESULT: result = src_alu_result;
default: result = 32'b0;
endcase