running c program

11 files changed, 145 insertions, 42 deletions

diff --git a/Makefile b/Makefile
index e7bfd27..dd0371b 100644
--- a/Makefile
+++ b/Makefile
@@ -47,7 +47,7 @@ RISCV_LD = $(RISCV_TOOLCHAIN)-ld
 RISCV_OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
 
 RISCV_ASFLAGS = -march=rv32i -mabi=ilp32
-RISCV_CFLAGS = -march=rv32i -mabi=ilp32 -O2 -Wall
+RISCV_CFLAGS = -march=rv32i -mabi=ilp32
 RISCV_LDFLAGS = -T prog/link.ld -m elf32lriscv
 
 PROG_SOURCE_DIR = prog/src
@@ -150,7 +150,7 @@ $(PROG_BINARY_FILE): $(PROG_ELF_FILE)
 
 # Convert the binary file to a hex file
 $(PROG_ROM_FILE): $(PROG_BINARY_FILE)
-	xxd -g 1 -c 1 -p $< > $@
+	xxd -g 4 -c 4 -p $< | awk '{print substr($$0,7,2) substr($$0,5,2) substr($$0,3,2) substr($$0,1,2)}' > $@
 
 # Create the build directory
 $(BUILD_DIR):
diff --git a/debug/cpu.gtkw b/debug/cpu.gtkw
index 919a1b1..92305c4 100644
--- a/debug/cpu.gtkw
+++ b/debug/cpu.gtkw
@@ -1,21 +1,22 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Mon May 13 05:19:11 2024
+[*] Wed May 15 06:26:49 2024
 [*]
 [dumpfile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/build/waveform_cpu.vcd"
-[dumpfile_mtime] "Mon May 13 05:16:41 2024"
-[dumpfile_size] 75516
+[dumpfile_mtime] "Wed May 15 06:25:06 2024"
+[dumpfile_size] 6805714
 [savefile] "/Users/flavian/Documents/hobbies/electronics/projects/riscv_cpu/debug/cpu.gtkw"
-[timestart] 3600
-[size] 1512 916
-[pos] 0 0
-*-15.000000 27100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[timestart] 36861700
+[size] 1512 945
+[pos] -1 -1
+*-15.000000 59800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] testbench_register_file.
 [treeopen] testbench_register_file.cpu.
+[treeopen] testbench_register_file.cpu.control_unit.
 [sst_width] 253
 [signals_width] 390
 [sst_expanded] 1
-[sst_vpaned_height] 278
+[sst_vpaned_height] 288
 @28
 testbench_register_file.clk
 testbench_register_file.rst
@@ -30,6 +31,11 @@ testbench_register_file.cpu.control_unit.state[3:0]
 testbench_register_file.cpu.instr_we
 @22
 testbench_register_file.cpu.instr[31:0]
+@28
+testbench_register_file.cpu.control_unit.opcode[6:0]
+testbench_register_file.cpu.control_unit.funct3[2:0]
+@22
+testbench_register_file.cpu.control_unit.funct7[6:0]
 @200
 -
 @22
@@ -45,8 +51,9 @@ testbench_register_file.cpu.pc_we
 -
 @22
 testbench_register_file.cpu.mem_addr[31:0]
-testbench_register_file.cpu.mem_rd[31:0]
 @23
+testbench_register_file.cpu.mem_rd[31:0]
+@22
 testbench_register_file.cpu.rd2_buf[31:0]
 @28
 testbench_register_file.cpu.mem_we
@@ -61,13 +68,12 @@ testbench_register_file.cpu.alu_a[31:0]
 testbench_register_file.cpu.alu_b[31:0]
 @28
 [color] 5
-testbench_register_file.cpu.alu_a_src[1:0]
-[color] 5
 testbench_register_file.cpu.alu_b_src[1:0]
 @22
 [color] 5
 testbench_register_file.cpu.alu_op[3:0]
 @28
+testbench_register_file.cpu.control_unit.alu_ctrl
 testbench_register_file.cpu.alu_zero
 @22
 [color] 5
diff --git a/prog/link.ld b/prog/link.ld
index 98658c3..4cc02ec 100644
--- a/prog/link.ld
+++ b/prog/link.ld
@@ -1,16 +1,67 @@
-OUTPUT_ARCH( "riscv" )
-ENTRY(_start)
+/* Linker script for RISC-V */
 
+/* Define memory regions */
 MEMORY
 {
-  ROM (rx)  : ORIGIN = 0x00010000, LENGTH = 0xF0000    # 0x0001_0000 - 0x000F_FFFF
-  RAM (rwx) : ORIGIN = 0x00100000, LENGTH = 0xFEFFFFF  # 0x0010_0000 - 0xFF0F_FFFF
+    ROM (rx)  : ORIGIN = 0x00010000, LENGTH = 0x400  /* 1024 bytes for ROM */
+    RAM (rwx) : ORIGIN = 0x00100000, LENGTH = 0x400  /* 1024 bytes for RAM */
 }
 
+ENTRY(_start)
+
+/* Define sections */
 SECTIONS
 {
-  .text  : { *(.text) }  > ROM
-  .data  : { *(.data) }  > RAM
-  .bss   : { *(.bss) }   > RAM
-  .stack : { *(.stack) } > RAM
+    /* Code section */
+    .text :
+    {
+        KEEP(*(.init))
+        KEEP(*(.text))
+        KEEP(*(.fini))
+        KEEP(*(.rodata))
+        _etext = .;
+    } > ROM
+
+    /* Initialized data section */
+    .data : AT(_etext)
+    {
+        _sdata = .;
+        KEEP(*(.data))
+        _edata = .;
+    } > RAM
+
+    /* Uninitialized data section */
+    .bss :
+    {
+        _sbss = .;
+        KEEP(*(.bss))
+        KEEP(*(COMMON))
+        _ebss = .;
+    } > RAM
+
+    /* Stack section */
+    .stack (NOLOAD) :
+    {
+        _stack_start = .;
+        . += 0x10; /* Adjust the size as needed */
+        _stack_end = .;
+    } > RAM
+
+    /* Heap section */
+    .heap (NOLOAD) :
+    {
+        _heap_start = .;
+        . += 0x10; /* Adjust the size as needed */
+        _heap_end = .;
+    } > RAM
 }
+
+/* Define symbols for memory initialization */
+PROVIDE(_start = 0x00010000);
+PROVIDE(_etext = _etext);
+PROVIDE(_sdata = _sdata);
+PROVIDE(_edata = _edata);
+PROVIDE(_sbss = _sbss);
+PROVIDE(_ebss = _ebss);
+PROVIDE(_sstack = _sstack);
+PROVIDE(_estack = _estack);
\ No newline at end of file
diff --git a/prog/src/main.c b/prog/src/main.c
new file mode 100644
index 0000000..1ce067c
--- /dev/null
+++ b/prog/src/main.c
@@ -0,0 +1,6 @@
+
+
+int main(void) {
+  while (1) {
+  }
+}
diff --git a/prog/src/prog.s b/prog/src/prog.s.bak
index 63026c9..63026c9 100644
--- a/prog/src/prog.s
+++ b/prog/src/prog.s.bak
diff --git a/prog/src/startup.s b/prog/src/startup.s
new file mode 100644
index 0000000..7adfb5e
--- /dev/null
+++ b/prog/src/startup.s
@@ -0,0 +1,42 @@
+.section .init
+.globl _start
+_start:
+    /* Set up stack pointer */
+    la sp, _stack_end
+
+    /* Initialize .data section (copy from LMA to VMA) */
+    la t0, _sdata       /* VMA start of .data */
+    la t1, _edata       /* VMA end of .data */
+    la t2, _etext       /* LMA start of .data in flash */
+copy_data:
+    beq t0, t1, clear_bss
+    lw t3, 0(t2)
+    sw t3, 0(t0)
+    addi t0, t0, 4
+    addi t2, t2, 4
+    j copy_data
+
+clear_bss:
+    /* Clear .bss section */
+    la t0, _sbss        /* VMA start of .bss */
+    la t1, _ebss        /* VMA end of .bss */
+clear_loop:
+    beq t0, t1, init_libc
+    sw x0, 0(t0)
+    addi t0, t0, 4
+    j clear_loop
+
+init_libc:
+    /* Call libc initialization functions */
+    /* call _init */
+
+    /* Call main function */
+    call main
+
+finalize_libc:
+    /* Call libc finalization functions */
+    /* call _fini */
+
+halt:
+    /* Infinite loop after main returns */
+    j halt
diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v
index 87b34d2..f227320 100644
--- a/sim/testbench_cpu.v
+++ b/sim/testbench_cpu.v
@@ -56,7 +56,7 @@ initial begin
   while (1) begin
     @(posedge clk);
     clk_cycle_count = clk_cycle_count + 1;
-    if (clk_cycle_count == 1000) $finish;
+    if (clk_cycle_count == 10000) $finish;
   end
 end
 
diff --git a/src/control_unit.v b/src/control_unit.v
index dfed9cc..28f37d9 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -104,7 +104,7 @@ always @ (*) begin
     STATE_JAL:       next_state = STATE_ALU_WB;
     STATE_JALR:      next_state = STATE_ALU_WB;
     STATE_LUI:       next_state = STATE_ALU_WB;
-    STATE_AUIPC:     next_state = STATE_FETCH;
+    STATE_AUIPC:     next_state = STATE_ALU_WB;
     STATE_BRANCH:    next_state = STATE_FETCH;
     default:         next_state = STATE_FETCH; 
   endcase
@@ -193,9 +193,6 @@ always @ (*) begin
       alu_a_src    = ALU_A_SRC_PC_BUF;
       alu_b_src    = ALU_B_SRC_IMM;
       alu_ctrl     = ALU_CTRL_ADD;
-      result_src   = RESULT_SRC_ALU_RESULT_BUF;
-      pc_update    = PC_UPDATE_ENABLE;
-
     end
     STATE_BRANCH: begin
       alu_a_src    = ALU_A_SRC_RD1_BUF;
diff --git a/src/memory_interface.v b/src/memory_interface.v
index 0fabc05..da06d1a 100644
--- a/src/memory_interface.v
+++ b/src/memory_interface.v
@@ -14,7 +14,7 @@ wire [31:0] ram_read_data, rom_read_data;
 
 ram #(.N(32), .SIZE(1024)) ram(
   .clk(clk),
-  .rst(!rstn),
+  .rstn(rstn),
   .we(ram_we),
   .addr(addr),
   .data_read(ram_read_data),
diff --git a/src/ram.v b/src/ram.v
index 3e5783d..91bb133 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -3,24 +3,21 @@ module ram #(
   parameter SIZE = 1024
 )(
     input clk,
-    input rst,
+    input rstn,
     input we,
-    input [log2(SIZE)-1:0] addr,
+    input [log2(SIZE/4)-1:0] addr,
     input [N-1:0] data_write,
-    output [N-1:0] data_read
+    output reg [N-1:0] data_read
 );
 
 `include "include/log2.vh"
 
-reg [8:0] memory [SIZE-1:0];
-
-assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
-
+//(* RAM_STYLE="BLOCK" *)
+reg [N-1:0] mem [SIZE-1:0];
 
 always @(posedge clk) begin
-  if (we) begin
-    { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } <= data_write;
-  end
+  if (we) mem[addr >> 2] <= data_write; 
+  data_read <= mem[addr >> 2];
 end
 
 endmodule
diff --git a/src/rom.v b/src/rom.v
index 381ca64..b317094 100644
--- a/src/rom.v
+++ b/src/rom.v
@@ -3,18 +3,22 @@ module rom #(
   parameter SIZE = 1024
 )(
     input clk,
-    input [log2(SIZE)-1:0] addr,
-    output [N-1:0] data_read
+    input [log2(SIZE/4)-1:0] addr,
+    output reg [N-1:0] data_read
 );
 
 `include "include/log2.vh"
 
-reg [7:0] memory [0:SIZE-1];
+
+//(* RAM_STYLE="BLOCK" *)
+reg [N-1:0] mem [SIZE-1:0];
 
 initial begin
-  $readmemh("build/rom.hex", memory, 0, SIZE-1);
+  $readmemh("build/rom.hex", mem, 0, SIZE/4-1);
 end
 
-assign data_read = {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
+always @(negedge clk) begin
+  data_read <= mem[addr >> 2];
+end
 
 endmodule