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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-02 08:11:36 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-02 08:11:36 +0200
commit3f3fd75006901cdd01a231785b6a2e43b5dc8a52 (patch)
treefce00b7f38ba89552d5a3f87722ea67ba9ba6047
parent1ee9b3d5a01c3d4fcc2b654cb695c324941379fc (diff)
downloadriscv_cpu-3f3fd75006901cdd01a231785b6a2e43b5dc8a52.tar.gz
riscv_cpu-3f3fd75006901cdd01a231785b6a2e43b5dc8a52.zip
register file
-rw-r--r--src/register_file.v41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/register_file.v b/src/register_file.v
new file mode 100644
index 0000000..4f09773
--- /dev/null
+++ b/src/register_file.v
@@ -0,0 +1,41 @@
+module register_file #(
+ parameter N = 32,
+ parameter XLEN = 32
+)(
+ input [CLOG2(XLEN)-1:0] A1, A2, A3,
+ input CLK,
+ input RST,
+ input WE3,
+ input [N-1:0] WD3,
+ output [N-1:0] RD1, RD2
+);
+
+ reg [N-1:0] registers[XLEN-1:0];
+
+ assign RD1 = A1 == 0 ? 0 : registers[A1];
+ assign RD2 = A2 == 0 ? 0 : registers[A2];
+
+ always @ (posedge CLK or negedge RST) begin
+ if (!RST) begin
+ integer i;
+ for (i = 0; i < XLEN; i = i + 1) begin
+ registers[i] <= 0;
+ end
+ end else if (WE3 && (A3 != 0)) begin
+ registers[A3] <= WD3;
+ end
+ end
+
+
+
+ function integer CLOG2(input integer value);
+ integer i;
+ begin
+ value = value - 1;
+ for (i = 0; value > 0; i = i + 1)
+ value = value >> 1;
+ CLOG2 = i;
+ end
+ endfunction
+
+endmodule