stopped initializing ram and register file to 0 at beginning

4 files changed, 26 insertions, 16 deletions

diff --git a/prog/src/prog.s b/prog/src/prog.s
index 8944306..4187c8a 100644
--- a/prog/src/prog.s
+++ b/prog/src/prog.s
@@ -47,9 +47,9 @@ _start:
 # sw    t1, 0(t0)
 # lw     t2, 0(t0)
 
-  addi t0, zero, -1
+  addi t0, zero, 1
   addi t1, zero, 2
-  bltu t0, t1, branch_taken
+  bge t0, t1, branch_taken
   addi t2, zero, 1
 
 
diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v
index a22f3e1..b0e0860 100644
--- a/sim/testbench_register_file.v
+++ b/sim/testbench_register_file.v
@@ -33,6 +33,7 @@ always #5 clk = ~clk;
 reg [1023:0] testvec_filename;
 reg [1023:0] waveform_filename;
 
+integer i;
 initial begin
   if ($value$plusargs("testvec=%s", testvec_filename)) begin
   end else begin
@@ -69,6 +70,14 @@ initial begin
   @(posedge clk);
   rst = 0;
 
+  for (i = 0; i < 32; i = i + 1) begin
+    we = 1;
+    addr_rd2 = i;
+    data_rd2 = 32'b0;
+    @(posedge clk);
+    #1;
+  end
+
   file = $fopen(testvec_filename, "r");
   if (file == 0) begin
     $display("ERROR: failed to open testvec");
diff --git a/src/ram.v b/src/ram.v
index 9b62c77..efcfc04 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -17,16 +17,16 @@ reg [8:0] memory [SIZE-1:0];
 assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
 
 
-integer i;
-always @(posedge clk or posedge rst) begin
-  if (rst) begin
-    for (i = 0; i < SIZE; i = i + 1)
-      memory[i] <= 0;
-  end else begin 
+// integer i;
+always @(posedge clk /*or posedge rst*/) begin
+//  if (rst) begin
+//    for (i = 0; i < SIZE; i = i + 1)
+//      memory[i] <= 0;
+//  end else begin 
     if (we) begin
       { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
     end
-  end
+//  end
 
 end
 
diff --git a/src/register_file.v b/src/register_file.v
index 58ba061..11c36fe 100644
--- a/src/register_file.v
+++ b/src/register_file.v
@@ -8,6 +8,7 @@ module register_file (
 
 reg [31:0] registers[31:1];
 
+// For debugging purposes:
 wire [31:0] reg_x0_zero,
             reg_x1_ra,
             reg_x2_sp,
@@ -75,18 +76,18 @@ assign reg_x30_t5 = registers[30];
 assign reg_x31_t6 = registers[31];
   
 
-integer i;
-always @(posedge clk or rst) begin
-    if (rst) begin
-    for (i = 1; i < 32; i = i + 1)
-      registers[i] <= 32'b0;
-  end else begin
+// integer i;
+always @(posedge clk /*or rst*/) begin
+//    if (rst) begin
+//    for (i = 1; i < 32; i = i + 1)
+//      registers[i] <= 32'b0;
+//  end else begin
     rs1_data = (rs1 == 0) ? 32'b0 : registers[rs1];
     rs2_data = (rs2 == 0) ? 32'b0 : registers[rs2];
     if (we && (rd != 0)) begin
       registers[rd] <= rd_data;
     end
-  end
+//  end
 end
 
 endmodule