assemble simple rom

17 files changed, 311 insertions, 1046 deletions

diff --git a/gentestvec/gentestvec_cpu.c b/gentestvec/gentestvec_cpu.c
new file mode 100644
index 0000000..8500dd9
--- /dev/null
+++ b/gentestvec/gentestvec_cpu.c
@@ -0,0 +1,6 @@
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <time.h>
+
+int main(int argc, const char *argv[]) { return 0; }
diff --git a/prog/build.sh b/prog/build.sh
new file mode 100755
index 0000000..22557b4
--- /dev/null
+++ b/prog/build.sh
@@ -0,0 +1,6 @@
+#!/bin/sh
+riscv64-unknown-elf-as -march=rv32i -mabi=ilp32 -o main.o main.s
+riscv64-unknown-elf-ld -T link.ld -m elf32lriscv -o main.elf main.o
+riscv64-unknown-elf-objcopy -O binary main.elf main.bin
+xxd -g 1 -c 1 -p main.bin >main.hex
+cp -f main.hex ../rom/rom.hex
diff --git a/prog/link.ld b/prog/link.ld
new file mode 100644
index 0000000..98658c3
--- /dev/null
+++ b/prog/link.ld
@@ -0,0 +1,16 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+MEMORY
+{
+  ROM (rx)  : ORIGIN = 0x00010000, LENGTH = 0xF0000    # 0x0001_0000 - 0x000F_FFFF
+  RAM (rwx) : ORIGIN = 0x00100000, LENGTH = 0xFEFFFFF  # 0x0010_0000 - 0xFF0F_FFFF
+}
+
+SECTIONS
+{
+  .text  : { *(.text) }  > ROM
+  .data  : { *(.data) }  > RAM
+  .bss   : { *(.bss) }   > RAM
+  .stack : { *(.stack) } > RAM
+}
diff --git a/prog/main.bin b/prog/main.bin
new file mode 100755
index 0000000..ba70022
--- /dev/null
+++ b/prog/main.bin
diff --git a/prog/main.elf b/prog/main.elf
new file mode 100755
index 0000000..4c53d74
--- /dev/null
+++ b/prog/main.elf
diff --git a/prog/main.hex b/prog/main.hex
new file mode 100644
index 0000000..116b9b4
--- /dev/null
+++ b/prog/main.hex
@@ -0,0 +1,16 @@
+93
+02
+50
+00
+13
+03
+30
+00
+b3
+83
+62
+00
+6f
+00
+00
+00
diff --git a/prog/main.o b/prog/main.o
new file mode 100644
index 0000000..e50c4a8
--- /dev/null
+++ b/prog/main.o
diff --git a/prog/main.s b/prog/main.s
new file mode 100644
index 0000000..bbae5bb
--- /dev/null
+++ b/prog/main.s
@@ -0,0 +1,24 @@
+.section .text
+.globl _start
+
+_start:
+  #la sp, stack_top
+    
+  #li a0, 10
+  #li a1, 20
+  #add a2, a0, a1
+  addi  t0, zero, 5
+  addi  t1, zero, 3
+  add   t2, t0,   t1
+
+halt_loop:
+  j halt_loop
+
+.section .data
+
+
+.section .bss
+
+.section .stack
+  .space 0x1000  # Allocate stack space
+stack_top:
diff --git a/rom/rom.hex b/rom/rom.hex
index 6ea4d64..116b9b4 100644
--- a/rom/rom.hex
+++ b/rom/rom.hex
@@ -1,1024 +1,16 @@
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diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v
new file mode 100644
index 0000000..ab3b31d
--- /dev/null
+++ b/sim/testbench_cpu.v
@@ -0,0 +1,64 @@
+`timescale 1ns / 1ps
+
+module testbench_register_file();
+
+reg clk;
+reg rst;
+
+cpu uut (
+  .clk(clk),
+  .rst(rst)
+);
+
+integer file, r, eof;
+reg [100*8:1] line;
+reg [31:0] test_count, error_count;
+
+
+always #5 clk = ~clk;
+
+reg [1023:0] testvec_filename;
+reg [1023:0] waveform_filename;
+
+initial begin
+  if ($value$plusargs("testvec=%s", testvec_filename)) begin
+  end else begin
+    $display("ERROR: testvec not specified");
+    $finish;
+  end
+
+  if ($value$plusargs("waveform=%s", waveform_filename)) begin
+  end else begin
+    $display("ERROR: waveform not specified");
+    $finish;
+  end
+end
+  
+initial begin
+  $dumpfile(waveform_filename);
+  $dumpvars(0,testbench_register_file);
+end
+
+
+initial begin
+  clk = 0;
+  rst = 0;
+  
+  test_count = 0;
+  error_count = 0;
+
+  @(negedge clk);
+  rst = 1;
+  @(negedge clk);
+  rst = 0;
+
+
+  while (1) begin
+    @(posedge clk);
+    test_count = test_count + 1;
+    if (test_count == 100) $finish;
+  end
+end
+
+endmodule
+
diff --git a/src/alu_op_decode.v b/src/alu_op_decode.v
index 64bb94b..8e801c8 100644
--- a/src/alu_op_decode.v
+++ b/src/alu_op_decode.v
@@ -1,5 +1,6 @@
 module alu_op_decode (
   input [6:0] opcode,
+  input [1:0] alu_ctrl,
   input [2:0] funct3,
   input [6:0] funct7,
   output reg [3:0] alu_op
diff --git a/src/control_unit.v b/src/control_unit.v
index a0d398a..d82db2a 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -6,14 +6,14 @@ module control_unit (
  input alu_zero,
  input alu_equal,
  output pc_we,
- output mem_addr_src,
- output mem_we,
- output instr_we,
- output [1:0] result_src,
+ output reg mem_addr_src,
+ output reg mem_we,
+ output reg instr_we,
+ output reg [1:0] result_src,
  output [3:0] alu_op,
- output [1:0] alu_a_src,
- output [1:0] alu_b_src,
- output rf_we
+ output reg [1:0] alu_a_src,
+ output reg [1:0] alu_b_src,
+ output reg rf_we
 );
 
 parameter s00_fetch     = 4'h0,
@@ -62,27 +62,89 @@ always @ (*) begin
   endcase
 end
 
-wire branch;
-wire pc_update;
+reg branch;
+reg pc_update;
+reg [1:0] alu_ctrl;
 
 assign pc_we = (alu_zero & branch) | pc_update;
 
-/*
+
 always @ (*) begin
- case(state)
-    s00_fetch:
-    s01_decode:
-    s02_mem_addr:
-    s03_mem_read:
-    s04_mem_wb:
-    s05_mem_write:
-    s06_execute_r:
-    s07_alu_wb:
-    s08_execute_i:
-    s09_jal:
-    s10_beq:
+  branch = 1'b0;
+  pc_update = 1'b0;
+  mem_we = 1'b0;
+  rf_we = 1'b0;
+  instr_we = 1'b0;
+  case(state)
+    s00_fetch: begin
+      mem_addr_src <= 1'b0;
+      instr_we      = 1'b1;
+      alu_a_src    <= 2'b00;
+      alu_b_src    <= 2'b10;
+      alu_ctrl     <= 2'b00;
+      result_src   <= 2'b10;
+      pc_update     = 1'b1;
+    end
+    s01_decode: begin
+      alu_a_src <= 2'b01;
+      alu_b_src <= 2'b01;
+      alu_ctrl  <= 2'b00;
+    end
+    s02_mem_addr: begin
+      alu_a_src <= 2'b10;
+      alu_b_src <= 2'b01;
+      alu_ctrl  <= 2'b00;
+    end
+    s03_mem_read: begin
+      result_src   <= 2'b00;
+      mem_addr_src <= 1'b1;
+    end
+    s04_mem_wb: begin
+      result_src <= 2'b01;
+      rf_we       = 1'b1;
+    end
+    s05_mem_write: begin
+      result_src   <= 2'b00;
+      mem_addr_src <= 1'b1;
+      mem_we        = 1'b1;
+    end
+    s06_execute_r: begin
+      alu_a_src <= 2'b10;
+      alu_b_src <= 2'b00;
+      alu_ctrl  <= 2'b10;
+    end
+    s07_alu_wb: begin
+      result_src <= 2'b00;
+      rf_we       = 1'b1;
+    end
+    s08_execute_i: begin
+      alu_a_src <= 2'b10;
+      alu_b_src <= 2'b01;
+      alu_ctrl  <= 2'b10;
+    end
+    s09_jal: begin
+      alu_a_src  <= 2'b01;
+      alu_b_src  <= 2'b10;
+      alu_ctrl   <= 2'b00;
+      result_src <= 2'b00;
+      pc_update   = 1'b1;
+    end
+    s10_beq: begin
+      alu_a_src  <= 2'b10;
+      alu_b_src  <= 2'b00;
+      alu_ctrl   <= 2'b01;
+      result_src <= 2'b00;
+      branch      = 1'b1;
+    end
   endcase
 end
-*/
+
+alu_op_decode aod (
+  .opcode(opcode),
+  .alu_ctrl(alu_ctrl),
+  .funct3(funct3),
+  .funct7(funct7),
+  .alu_op(alu_op)
+);
 
 endmodule
diff --git a/src/cpu.v b/src/cpu.v
index c6f9f9e..b839477 100644
--- a/src/cpu.v
+++ b/src/cpu.v
@@ -7,6 +7,7 @@ module cpu (
 // Control Unit
 
 wire mem_addr_src;
+wire mem_we;
 wire pc_we;
 wire instr_we;
 wire rf_we;
diff --git a/src/ram.v b/src/ram.v
index f92c66f..92b14a2 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -21,9 +21,9 @@ always @(posedge clk or posedge rst) begin
       memory[i] <= 0;
   end else begin
     if (we) begin
-      memory[addr] = data_write;
+      { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
     end
-    data_read = memory[addr];
+    data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
   end
 
 end
diff --git a/src/register_file.v b/src/register_file.v
index 5142a69..58ba061 100644
--- a/src/register_file.v
+++ b/src/register_file.v
@@ -8,9 +8,76 @@ module register_file (
 
 reg [31:0] registers[31:1];
 
+wire [31:0] reg_x0_zero,
+            reg_x1_ra,
+            reg_x2_sp,
+            reg_x3_gp,
+            reg_x4_tp,
+            reg_x5_t0,
+            reg_x6_t1,
+            reg_x7_t2,
+            reg_x8_s0_fp,
+            reg_x9_s1,
+            reg_x10_a0,
+            reg_x11_a1,
+            reg_x12_a2,
+            reg_x13_a3,
+            reg_x14_a4,
+            reg_x15_a5,
+            reg_x16_a6,
+            reg_x17_a7,
+            reg_x18_s2,
+            reg_x19_s3,
+            reg_x20_s4,
+            reg_x21_s5,
+            reg_x22_s6,
+            reg_x23_s7,
+            reg_x24_s8,
+            reg_x25_s9,
+            reg_x26_s10,
+            reg_x27_s11,
+            reg_x28_t3,
+            reg_x29_t4,
+            reg_x30_t5,
+            reg_x31_t6;
+
+assign reg_x0_zero = 32'b0;
+assign reg_x1_ra = registers[1];
+assign reg_x2_sp = registers[2];
+assign reg_x3_gp = registers[3];
+assign reg_x4_tp = registers[4];
+assign reg_x5_t0 = registers[5];
+assign reg_x6_t1 = registers[6];
+assign reg_x7_t2 = registers[7];
+assign reg_x8_s0_fp = registers[8];
+assign reg_x9_s1 = registers[9];
+assign reg_x10_a0 = registers[10];
+assign reg_x11_a1 = registers[11];
+assign reg_x12_a2 = registers[12];
+assign reg_x13_a3 = registers[13];
+assign reg_x14_a4 = registers[14];
+assign reg_x15_a5 = registers[15];
+assign reg_x16_a6 = registers[16];
+assign reg_x17_a7 = registers[17];
+assign reg_x18_s2 = registers[18];
+assign reg_x19_s3 = registers[19];
+assign reg_x20_s4 = registers[20];
+assign reg_x21_s5 = registers[21];
+assign reg_x22_s6 = registers[22];
+assign reg_x23_s7 = registers[23];
+assign reg_x24_s8 = registers[24];
+assign reg_x25_s9 = registers[25];
+assign reg_x26_s10 = registers[26];
+assign reg_x27_s11 = registers[27];
+assign reg_x28_t3 = registers[28];
+assign reg_x29_t4 = registers[29];
+assign reg_x30_t5 = registers[30];
+assign reg_x31_t6 = registers[31];
+  
+
 integer i;
 always @(posedge clk or rst) begin
-  if (rst) begin
+    if (rst) begin
     for (i = 1; i < 32; i = i + 1)
       registers[i] <= 32'b0;
   end else begin
diff --git a/src/rom.v b/src/rom.v
index aa8c359..0a00479 100644
--- a/src/rom.v
+++ b/src/rom.v
@@ -9,14 +9,14 @@ module rom #(
 
 `include "include/log2.vh"
 
-reg [7:0] memory [SIZE-1:0];
+reg [7:0] memory [0:SIZE-1];
 
 initial begin
   $readmemh("rom/rom.hex", memory, 0, SIZE-1);
 end
 
 always @(posedge clk) begin
-  data_read = memory[addr];
+  data_read <= {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
 end
 
 
diff --git a/src/top.v b/src/top.v
index 845b17c..37e33d7 100644
--- a/src/top.v
+++ b/src/top.v
@@ -1,9 +1,19 @@
 module top (
 	input clk,
-	input key,
-	output [5:0] led
+	input key
+	//output [5:0] led
 );
 
+wire rst;
+assign rst = ~key;
+
+cpu cpu (
+  .clk(clk),
+  .rst(rst)
+);
+
+/*
+
 reg [5:0] ctr_q;
 wire [5:0] ctr_d;
 wire clk_slow;
@@ -22,5 +32,5 @@ end
 
 assign ctr_d = ctr_q + 6'b1;
 assign led = ~ctr_q;
-
+*/
 endmodule