bug fixes

17 files changed, 222 insertions, 128 deletions

diff --git a/include/consts.vh b/include/consts.vh
index 8c31c7d..952b0de 100644
--- a/include/consts.vh
+++ b/include/consts.vh
@@ -1,7 +1,8 @@
-parameter ALU_A_SRC_PC      = 2'b00;
-parameter ALU_A_SRC_PC_BUF  = 2'b01;
-parameter ALU_A_SRC_RD1_BUF = 2'b10;
-parameter ALU_A_SRC_0       = 2'b11;
+parameter ALU_A_SRC_PC      = 3'b000;
+parameter ALU_A_SRC_PC_BUF  = 3'b001;
+parameter ALU_A_SRC_RD1_BUF = 3'b010;
+parameter ALU_A_SRC_RD1     = 3'b011;
+parameter ALU_A_SRC_0       = 3'b100;
 
 parameter ALU_B_SRC_RD2_BUF = 2'b00;
 parameter ALU_B_SRC_IMM     = 2'b01;
diff --git a/prog/src/prog.s b/prog/src/prog.s
index 128af52..63026c9 100644
--- a/prog/src/prog.s
+++ b/prog/src/prog.s
@@ -3,7 +3,12 @@
 
 _start:
 
+ 
+ j test_prog
+
 
+
+/*
   addi t0, zero, 31
 reset_loop:
   addi t6, zero, 0
@@ -11,11 +16,78 @@ loop:
   addi t6, t6, 1
   beq t6, t0, reset_loop
   j loop
-
+*/
 
 halt_loop:
   j halt_loop
 
+test_prog:
+  li t0, 0xFFFFFFFF
+  li t1, 0x33333333
+  li t2, 0x88888888
+  li t3, 0x11111111
+
+  add   t4, t1,   t2
+  sub   t4, t1,   t2
+  slt   t4, t3,   t0
+  slt   t4, t0,   t3
+  sltu  t4, t3,   t0
+  sltu  t4, t0,   t3
+  and   t4, zero, zero
+  and   t4, zero, t0
+  and   t4, t0,   t0
+  or    t4, zero, zero
+  or    t4, zero, t0
+  or    t4, t0,   t0
+  xor   t4, zero, zero
+  xor   t4, zero, t0
+  xor   t4, t0,   t0
+  
+  beq   t0, t0, branch_eq
+  j branch_eq_nt
+
+branch_eq_ret:
+  beq   t0, t3, branch_ne
+  j branch_ne_nt
+
+branch_ne_ret:
+  call func
+
+  li  t0, 0x00100000 
+  sw  t1, 0(t0)
+  lw  t2, 0(t0)
+
+  j halt_loop
+
+
+branch_eq:
+  addi  t5, zero, 1
+  j branch_eq_ret
+
+branch_eq_nt:
+  addi  t5, zero, 2
+  j branch_eq_ret
+
+branch_ne:
+  addi  t5, zero, 3
+  j branch_ne_ret
+
+branch_ne_nt:
+  addi  t5, zero, 4
+  j branch_ne_ret
+
+func:
+  addi  t5, zero, 5
+  ret
+
+
+
+
+
+
+
+
+
  
 .section .data
 
diff --git a/src/alu.v b/src/alu.v
index 839128e..8a265ee 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -35,10 +35,10 @@ shift_unit su (
 
 always @ (*) begin
   case (op[3:2])
-    ALU_OP_ARITHMETIC: result <= arithmetic_result; // ARITHMETIC
-    ALU_OP_LOGIC:      result <= logic_result;      // LOGIC
-    ALU_OP_SHIFT:      result <= shift_result;      // SHIFT
-    default:           result <= 31'b0;
+    ALU_OP_ARITHMETIC: result = arithmetic_result; // ARITHMETIC
+    ALU_OP_LOGIC:      result = logic_result;      // LOGIC
+    ALU_OP_SHIFT:      result = shift_result;      // SHIFT
+    default:           result = 31'b0;
   endcase
 end
 
diff --git a/src/alu_a_src_mux.v b/src/alu_a_src_mux.v
index 208cc82..8998b55 100644
--- a/src/alu_a_src_mux.v
+++ b/src/alu_a_src_mux.v
@@ -2,8 +2,9 @@ module alu_a_src_mux (
   input [31:0] src_pc, 
   input [31:0] src_pc_buf, 
   input [31:0] src_rd1_buf,
+  input [31:0] src_rd1,
 
-  input [1:0] alu_a_src,
+  input [2:0] alu_a_src,
 
   output reg [31:0] alu_a
 );
@@ -12,11 +13,12 @@ module alu_a_src_mux (
 
 always @(*) begin
   case (alu_a_src)
-    ALU_A_SRC_PC:      alu_a <= src_pc;
-    ALU_A_SRC_PC_BUF:  alu_a <= src_pc_buf;
-    ALU_A_SRC_RD1_BUF: alu_a <= src_rd1_buf;
-    ALU_A_SRC_0:       alu_a <= 32'b0;
-    default:           alu_a <= 32'b0;
+    ALU_A_SRC_PC:      alu_a = src_pc;
+    ALU_A_SRC_PC_BUF:  alu_a = src_pc_buf;
+    ALU_A_SRC_RD1_BUF: alu_a = src_rd1_buf;
+    ALU_A_SRC_RD1:     alu_a = src_rd1;
+    ALU_A_SRC_0:       alu_a = 32'b0;
+    default:           alu_a = 32'b0;
   endcase
 end
 
diff --git a/src/alu_b_src_mux.v b/src/alu_b_src_mux.v
index 615d312..5932f9e 100644
--- a/src/alu_b_src_mux.v
+++ b/src/alu_b_src_mux.v
@@ -11,10 +11,10 @@ module alu_b_src_mux (
 
 always @(*) begin
   case (alu_b_src)
-    ALU_B_SRC_RD2_BUF: alu_b <= src_rd2_buf;
-    ALU_B_SRC_IMM:     alu_b <= src_imm;
-    ALU_B_SRC_4:       alu_b <= 32'h4;
-    default:           alu_b <= 32'b0;
+    ALU_B_SRC_RD2_BUF: alu_b = src_rd2_buf;
+    ALU_B_SRC_IMM:     alu_b = src_imm;
+    ALU_B_SRC_4:       alu_b = 32'h4;
+    default:           alu_b = 32'b0;
   endcase
 end
 
diff --git a/src/alu_op_decode.v b/src/alu_op_decode.v
index 0e217ec..4523255 100644
--- a/src/alu_op_decode.v
+++ b/src/alu_op_decode.v
@@ -12,31 +12,31 @@ module alu_op_decode (
 
 always @ (*) begin
   if (alu_ctrl == ALU_CTRL_ADD) begin
-    alu_op <= ALU_OP_ADD;
+    alu_op = ALU_OP_ADD;
   end else if (opcode == OPCODE_REG || opcode == OPCODE_IMM) begin
     case (funct3)
-      FUNCT3_ALU_ADD_SUB: alu_op <= (opcode == OPCODE_REG || funct7 == FUNCT7_ALU_SUB) ? ALU_OP_SUB : ALU_OP_ADD;
-      FUNCT3_ALU_SLL:     alu_op <= ALU_OP_SLL;
-      FUNCT3_ALU_SLT:     alu_op <= ALU_OP_SLT;
-      FUNCT3_ALU_SLTU:    alu_op <= ALU_OP_SLTU;
-      FUNCT3_ALU_XOR:     alu_op <= ALU_OP_XOR;
-      FUNCT3_ALU_SR:      alu_op <= funct7 == FUNCT7_ALU_SRL ? ALU_OP_SRL : ALU_OP_SRA;
-      FUNCT3_ALU_OR:      alu_op <= ALU_OP_OR;
-      FUNCT3_ALU_AND:     alu_op <= ALU_OP_AND;
-      default:            alu_op <= ALU_OP_ADD;
+      FUNCT3_ALU_ADD_SUB: alu_op = (opcode == OPCODE_REG && funct7 == FUNCT7_ALU_SUB) ? ALU_OP_SUB : ALU_OP_ADD;
+      FUNCT3_ALU_SLL:     alu_op = ALU_OP_SLL;
+      FUNCT3_ALU_SLT:     alu_op = ALU_OP_SLT;
+      FUNCT3_ALU_SLTU:    alu_op = ALU_OP_SLTU;
+      FUNCT3_ALU_XOR:     alu_op = ALU_OP_XOR;
+      FUNCT3_ALU_SR:      alu_op = funct7 == FUNCT7_ALU_SRL ? ALU_OP_SRL : ALU_OP_SRA;
+      FUNCT3_ALU_OR:      alu_op = ALU_OP_OR;
+      FUNCT3_ALU_AND:     alu_op = ALU_OP_AND;
+      default:            alu_op = ALU_OP_ADD;
     endcase
   end else if (opcode == OPCODE_BRANCH) begin
     case (funct3)
-      FUNCT3_BRANCH_BEQ:  alu_op <= ALU_OP_SUB;
-      FUNCT3_BRANCH_BNE:  alu_op <= ALU_OP_SUB;
-      FUNCT3_BRANCH_BLT:  alu_op <= ALU_OP_SLT;
-      FUNCT3_BRANCH_BGE:  alu_op <= ALU_OP_SLT;
-      FUNCT3_BRANCH_BLTU: alu_op <= ALU_OP_SLTU;
-      FUNCT3_BRANCH_BGEU: alu_op <= ALU_OP_SLTU;
-      default:            alu_op <= ALU_OP_ADD;
+      FUNCT3_BRANCH_BEQ:  alu_op = ALU_OP_SUB;
+      FUNCT3_BRANCH_BNE:  alu_op = ALU_OP_SUB;
+      FUNCT3_BRANCH_BLT:  alu_op = ALU_OP_SLT;
+      FUNCT3_BRANCH_BGE:  alu_op = ALU_OP_SLT;
+      FUNCT3_BRANCH_BLTU: alu_op = ALU_OP_SLTU;
+      FUNCT3_BRANCH_BGEU: alu_op = ALU_OP_SLTU;
+      default:            alu_op = ALU_OP_ADD;
     endcase
   end else begin
-    alu_op <= ALU_OP_ADD;
+    alu_op = ALU_OP_ADD;
   end
 end
 
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v
index 2ac302e..1a2282b 100644
--- a/src/arithmetic_unit.v
+++ b/src/arithmetic_unit.v
@@ -16,11 +16,11 @@ assign b_signed = b;
 
 always @ (*) begin
   case (op)
-    ARITHMETIC_OP_ADD:  result <= a + b;                               // ADD
-    ARITHMETIC_OP_SUB:  result <= a - b;                               // SUB
-    ARITHMETIC_OP_SLT:  result <= { {31{1'b0}}, a_signed < b_signed }; // SLT
-    ARITHMETIC_OP_SLTU: result <= { {31{1'b0}}, a < b };               // SLTU
-    default:            result <= 32'b0;
+    ARITHMETIC_OP_ADD:  result = a + b;                               // ADD
+    ARITHMETIC_OP_SUB:  result = a - b;                               // SUB
+    ARITHMETIC_OP_SLT:  result = { {31{1'b0}}, a_signed < b_signed }; // SLT
+    ARITHMETIC_OP_SLTU: result = { {31{1'b0}}, a < b };               // SLTU
+    default:            result = 32'b0;
   endcase
 end
 
diff --git a/src/control_unit.v b/src/control_unit.v
index 9a5b413..dfed9cc 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -16,7 +16,7 @@ module control_unit (
  output reg rf_we,
  output [4:0] ra1, ra2, wa3,
 
- output reg [1:0] alu_a_src,
+ output reg [2:0] alu_a_src,
  output reg [1:0] alu_b_src,
  output [3:0] alu_op,
 
@@ -29,6 +29,10 @@ wire [6:0] opcode;
 wire [2:0] funct3;
 wire [6:0] funct7;
 
+reg branch;
+reg pc_update;
+reg alu_ctrl;
+
 assign opcode = instr[6:0];
 assign funct3 = instr[14:12];
 assign funct7 = instr[31:25];
@@ -37,26 +41,35 @@ assign ra1 = instr[19:15];
 assign ra2 = instr[24:20];
 assign wa3 = instr[11:7];
 
+assign pc_we = ((alu_zero ^ funct3[0] ^ funct3[2]) & branch) | pc_update;
+
+reg [3:0] state, next_state;
+
+alu_op_decode alu_op_decode (
+  .opcode(opcode),
+  .alu_ctrl(alu_ctrl),
+  .funct3(funct3),
+  .funct7(funct7),
+  .alu_op(alu_op)
+);
 
 always @ (*) begin
   case (opcode)
-    OPCODE_REG:    imm_src <= INSTR_FORMAT_R; // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
-    OPCODE_IMM:    imm_src <= INSTR_FORMAT_I; // ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
-    OPCODE_LOAD:   imm_src <= INSTR_FORMAT_I; // LB, LH, LW, LBU, LHU
-    OPCODE_JALR:   imm_src <= INSTR_FORMAT_I; // JALR
-    OPCODE_STORE:  imm_src <= INSTR_FORMAT_S; // SB, SH, SW
-    OPCODE_BRANCH: imm_src <= INSTR_FORMAT_B; // BEQ, BNE, BLT, BGE, BLTU, BGEU
-    OPCODE_LUI:    imm_src <= INSTR_FORMAT_U; // LUI
-    OPCODE_AUIPC:  imm_src <= INSTR_FORMAT_U; // AUIPC
-    OPCODE_JAL:    imm_src <= INSTR_FORMAT_J; // JAL
-    OPCODE_SYNC:   imm_src <= INSTR_FORMAT_I; // FENCE
-    OPCODE_SYS:    imm_src <= INSTR_FORMAT_I; // ECALL, EBREAK
-    default:       imm_src <= INSTR_FORMAT_UNKNOWN;
+    OPCODE_REG:    imm_src = INSTR_FORMAT_R; // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
+    OPCODE_IMM:    imm_src = INSTR_FORMAT_I; // ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
+    OPCODE_LOAD:   imm_src = INSTR_FORMAT_I; // LB, LH, LW, LBU, LHU
+    OPCODE_JALR:   imm_src = INSTR_FORMAT_I; // JALR
+    OPCODE_STORE:  imm_src = INSTR_FORMAT_S; // SB, SH, SW
+    OPCODE_BRANCH: imm_src = INSTR_FORMAT_B; // BEQ, BNE, BLT, BGE, BLTU, BGEU
+    OPCODE_LUI:    imm_src = INSTR_FORMAT_U; // LUI
+    OPCODE_AUIPC:  imm_src = INSTR_FORMAT_U; // AUIPC
+    OPCODE_JAL:    imm_src = INSTR_FORMAT_J; // JAL
+    OPCODE_SYNC:   imm_src = INSTR_FORMAT_I; // FENCE
+    OPCODE_SYS:    imm_src = INSTR_FORMAT_I; // ECALL, EBREAK
+    default:       imm_src = INSTR_FORMAT_UNKNOWN;
   endcase
 end
 
-reg [3:0] state, next_state;
-
 always @ (posedge clk or negedge rstn) begin
   if (!rstn) state <= STATE_FETCH;
   else state <= next_state;
@@ -64,40 +77,40 @@ end
 
 always @ (*) begin
   case(state)
-    STATE_FETCH:     next_state <= STATE_DECODE;
+    STATE_FETCH:     next_state = STATE_DECODE;
     STATE_DECODE: case(opcode)
-      OPCODE_LOAD:   next_state <= STATE_MEM_ADDR;
-      OPCODE_STORE:  next_state <= STATE_MEM_ADDR;
-      OPCODE_REG:    next_state <= STATE_EXECUTE_R;
-      OPCODE_IMM:    next_state <= STATE_EXECUTE_I;
-      OPCODE_JAL:    next_state <= STATE_JAL;
-      OPCODE_JALR:   next_state <= STATE_JALR;
-      OPCODE_BRANCH: next_state <= STATE_BRANCH;
-      default:       next_state <= STATE_FETCH;
+      OPCODE_LOAD:   next_state = STATE_MEM_ADDR;
+      OPCODE_STORE:  next_state = STATE_MEM_ADDR;
+      OPCODE_REG:    next_state = STATE_EXECUTE_R;
+      OPCODE_IMM:    next_state = STATE_EXECUTE_I;
+      OPCODE_JAL:    next_state = STATE_JAL;
+      OPCODE_JALR:   next_state = STATE_JALR;
+      OPCODE_LUI:    next_state = STATE_LUI;
+      OPCODE_AUIPC:  next_state = STATE_AUIPC;
+      OPCODE_BRANCH: next_state = STATE_BRANCH;
+      default:       next_state = STATE_FETCH;
     endcase
     STATE_MEM_ADDR:  case(opcode)
-      OPCODE_LOAD:   next_state <= STATE_MEM_LOAD;
-      OPCODE_STORE:  next_state <= STATE_MEM_STORE; 
-      default:       next_state <= STATE_FETCH;
+      OPCODE_LOAD:   next_state = STATE_MEM_LOAD;
+      OPCODE_STORE:  next_state = STATE_MEM_STORE; 
+      default:       next_state = STATE_FETCH;
     endcase
-    STATE_MEM_LOAD:  next_state <= STATE_MEM_WB;
-    STATE_MEM_WB:    next_state <= STATE_FETCH;
-    STATE_MEM_STORE: next_state <= STATE_FETCH;
-    STATE_EXECUTE_R: next_state <= STATE_ALU_WB;
-    STATE_ALU_WB:    next_state <= STATE_FETCH;
-    STATE_EXECUTE_I: next_state <= STATE_ALU_WB;
-    STATE_JAL:       next_state <= STATE_ALU_WB;
-    STATE_JALR:      next_state <= STATE_ALU_WB;
-    STATE_BRANCH:    next_state <= STATE_FETCH;
-    default:         next_state <= STATE_FETCH; 
+    STATE_MEM_LOAD:  next_state = STATE_MEM_WB;
+    STATE_MEM_WB:    next_state = STATE_FETCH;
+    STATE_MEM_STORE: next_state = STATE_FETCH;
+    STATE_EXECUTE_R: next_state = STATE_ALU_WB;
+    STATE_ALU_WB:    next_state = STATE_FETCH;
+    STATE_EXECUTE_I: next_state = STATE_ALU_WB;
+    STATE_JAL:       next_state = STATE_ALU_WB;
+    STATE_JALR:      next_state = STATE_ALU_WB;
+    STATE_LUI:       next_state = STATE_ALU_WB;
+    STATE_AUIPC:     next_state = STATE_FETCH;
+    STATE_BRANCH:    next_state = STATE_FETCH;
+    default:         next_state = STATE_FETCH; 
   endcase
 end
 
-reg branch;
-reg pc_update;
-reg alu_ctrl;
 
-assign pc_we = ((alu_zero ^ funct3[0] ^ funct3[2]) & branch) | pc_update;
 
 always @ (*) begin
   mem_addr_src = MEM_ADDR_SRC_RESULT;
@@ -121,7 +134,7 @@ always @ (*) begin
       pc_update    = PC_UPDATE_ENABLE;
     end
     STATE_DECODE: begin
-      alu_a_src    = ALU_A_SRC_PC_BUF;
+      alu_a_src    = (opcode == OPCODE_JALR) ? ALU_A_SRC_RD1 : ALU_A_SRC_PC_BUF;
       alu_b_src    = ALU_B_SRC_IMM;
       alu_ctrl     = ALU_CTRL_ADD;
     end
@@ -165,11 +178,24 @@ always @ (*) begin
       pc_update    = PC_UPDATE_ENABLE;
     end
     STATE_JALR: begin
-      alu_a_src    = ALU_A_SRC_RD1_BUF;
+      alu_a_src    = ALU_A_SRC_PC_BUF;
+      alu_b_src    = ALU_B_SRC_4;
+      alu_ctrl     = ALU_CTRL_ADD;
+      result_src   = RESULT_SRC_ALU_RESULT_BUF;
+      pc_update    = PC_UPDATE_ENABLE;
+    end
+    STATE_LUI: begin
+      alu_a_src    = ALU_A_SRC_0;
       alu_b_src    = ALU_B_SRC_IMM;
       alu_ctrl     = ALU_CTRL_ADD;
-      result_src   = RESULT_SRC_ALU_RESULT;
+    end
+    STATE_AUIPC: begin
+      alu_a_src    = ALU_A_SRC_PC_BUF;
+      alu_b_src    = ALU_B_SRC_IMM;
+      alu_ctrl     = ALU_CTRL_ADD;
+      result_src   = RESULT_SRC_ALU_RESULT_BUF;
       pc_update    = PC_UPDATE_ENABLE;
+
     end
     STATE_BRANCH: begin
       alu_a_src    = ALU_A_SRC_RD1_BUF;
@@ -181,12 +207,4 @@ always @ (*) begin
   endcase
 end
 
-alu_op_decode alu_op_decode (
-  .opcode(opcode),
-  .alu_ctrl(alu_ctrl),
-  .funct3(funct3),
-  .funct7(funct7),
-  .alu_op(alu_op)
-);
-
 endmodule
diff --git a/src/cpu.v b/src/cpu.v
index b6e3f51..e3c3eb5 100644
--- a/src/cpu.v
+++ b/src/cpu.v
@@ -27,7 +27,7 @@ wire [31:0] rd1, rd2;
 wire [31:0] rd1_buf, rd2_buf;
 
 wire [31:0] alu_a, alu_b;
-wire [1:0] alu_a_src;
+wire [2:0] alu_a_src;
 wire [1:0] alu_b_src;
 wire [3:0] alu_op;
 wire [31:0] alu_result;
@@ -131,6 +131,7 @@ register_file_reg register_file_reg (
 alu_a_src_mux alu_a_src_mux(
   .src_pc(pc),
   .src_pc_buf(pc_buf),
+  .src_rd1(rd1),
   .src_rd1_buf(rd1_buf),
   .alu_a_src(alu_a_src),
   .alu_a(alu_a)
diff --git a/src/immediate_extend.v b/src/immediate_extend.v
index 6e39e7d..14a9a33 100644
--- a/src/immediate_extend.v
+++ b/src/immediate_extend.v
@@ -9,12 +9,12 @@ module immediate_extend (
 
 always @ (*) begin
   case (imm_src)
-    INSTR_FORMAT_I:  imm <= { {21{instr[31]}}, instr[30:20] };                                // I
-    INSTR_FORMAT_S:  imm <= { {21{instr[31]}}, instr[30:25], instr[11:7] };                   // S
-    INSTR_FORMAT_B:  imm <= { {20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0 };   // B
-    INSTR_FORMAT_U:  imm <= { instr[31:12], 12'b0 };                                          // U
-    INSTR_FORMAT_J:  imm <= { {12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }; // J
-    default:         imm <= 32'b0;                                                            // Unknown
+    INSTR_FORMAT_I:  imm = { {21{instr[31]}}, instr[30:20] };                                // I
+    INSTR_FORMAT_S:  imm = { {21{instr[31]}}, instr[30:25], instr[11:7] };                   // S
+    INSTR_FORMAT_B:  imm = { {20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0 };   // B
+    INSTR_FORMAT_U:  imm = { instr[31:12], 12'b0 };                                          // U
+    INSTR_FORMAT_J:  imm = { {12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }; // J
+    default:         imm = 32'b0;                                                            // Unknown
   endcase
 end
 
diff --git a/src/logic_unit.v b/src/logic_unit.v
index ca858d0..8d8b31d 100644
--- a/src/logic_unit.v
+++ b/src/logic_unit.v
@@ -11,10 +11,10 @@ module logic_unit (
   
 always @ (*) begin
   case (op)
-    LOGIC_OP_AND: result <= a & b; // AND
-    LOGIC_OP_OR:  result <= a | b; // OR
-    LOGIC_OP_XOR: result <= a ^ b; // XOR
-    default:      result <= 32'b0;
+    LOGIC_OP_AND: result = a & b; // AND
+    LOGIC_OP_OR:  result = a | b; // OR
+    LOGIC_OP_XOR: result = a ^ b; // XOR
+    default:      result = 32'b0;
   endcase
 end
 
diff --git a/src/mem_addr_src_mux.v b/src/mem_addr_src_mux.v
index 633b345..1f34fe1 100644
--- a/src/mem_addr_src_mux.v
+++ b/src/mem_addr_src_mux.v
@@ -11,9 +11,9 @@ module mem_addr_src_mux (
 
 always @(*) begin
   case (mem_addr_src)
-    MEM_ADDR_SRC_PC:     mem_addr <= src_pc;
-    MEM_ADDR_SRC_RESULT: mem_addr <= src_result;
-    default:             mem_addr <= 32'b0;
+    MEM_ADDR_SRC_PC:     mem_addr = src_pc;
+    MEM_ADDR_SRC_RESULT: mem_addr = src_result;
+    default:             mem_addr = 32'b0;
   endcase
 end
 
diff --git a/src/memory_interface.v b/src/memory_interface.v
index 0ea837a..0fabc05 100644
--- a/src/memory_interface.v
+++ b/src/memory_interface.v
@@ -12,7 +12,7 @@ module memory_interface (
 reg ram_we;
 wire [31:0] ram_read_data, rom_read_data;
 
-ram #(.N(32), .SIZE(16)) ram(
+ram #(.N(32), .SIZE(1024)) ram(
   .clk(clk),
   .rst(!rstn),
   .we(ram_we),
@@ -21,7 +21,7 @@ ram #(.N(32), .SIZE(16)) ram(
   .data_write(wd)
 );
 
-rom #(.N(32), .SIZE(32)) rom(
+rom #(.N(32), .SIZE(1024)) rom(
   .clk(clk),
   .addr(addr),
   .data_read(rom_read_data)
@@ -43,17 +43,17 @@ rom #(.N(32), .SIZE(32)) rom(
 
 always @(*) begin
   if (addr[31:16] >= 16'h0001 && addr[31:16] <= 16'h000F) begin
-    ram_we <= 0;
-    rd <= rom_read_data;
+    ram_we = 0;
+    rd = rom_read_data;
   end else if (addr[31:16] >= 16'h0010 && addr[31:16] <= 16'hFF0F) begin
-    ram_we <= we;
-    rd <= ram_read_data;
+    ram_we = we;
+    rd = ram_read_data;
   end else if (addr[31:16] >= 16'hFF10 && addr[31:16] <= 16'hFFFF) begin
-    ram_we <= 0;
-    rd <= 0;
+    ram_we = 0;
+    rd = 0;
   end else begin
-    ram_we <= 0;
-    rd <= 0;
+    ram_we = 0;
+    rd = 0;
   end
 end
 
diff --git a/src/ram.v b/src/ram.v
index 8234d5d..3e5783d 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -19,7 +19,7 @@ assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memor
 
 always @(posedge clk) begin
   if (we) begin
-    { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
+    { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } <= data_write;
   end
 end
 
diff --git a/src/register_file.v b/src/register_file.v
index 12a0433..7f83704 100644
--- a/src/register_file.v
+++ b/src/register_file.v
@@ -91,7 +91,7 @@ assign rd1 = ra1 == 0 ? 32'b0 : regs[ra1];
 assign rd2 = ra2 == 0 ? 32'b0 : regs[ra2];
 
 always @ (posedge clk) begin
-  if (we && (wa3 != 0)) regs[wa3] = wd3;
+  if (we && (wa3 != 0)) regs[wa3] <= wd3;
 end
 
 endmodule
diff --git a/src/result_mux.v b/src/result_mux.v
index 528913d..9aab115 100644
--- a/src/result_mux.v
+++ b/src/result_mux.v
@@ -12,10 +12,10 @@ module result_mux (
 
 always @(*) begin
   case (result_src)
-    RESULT_SRC_ALU_RESULT_BUF: result <= src_alu_result_buf;
-    RESULT_SRC_DATA_BUF:       result <= src_data_buf;
-    RESULT_SRC_ALU_RESULT:     result <= src_alu_result;
-    default:                   result <= 32'b0;
+    RESULT_SRC_ALU_RESULT_BUF: result = src_alu_result_buf;
+    RESULT_SRC_DATA_BUF:       result = src_data_buf;
+    RESULT_SRC_ALU_RESULT:     result = src_alu_result;
+    default:                   result = 32'b0;
   endcase
 end
 
diff --git a/src/shift_unit.v b/src/shift_unit.v
index e92334d..ea83e4a 100644
--- a/src/shift_unit.v
+++ b/src/shift_unit.v
@@ -11,10 +11,10 @@ module shift_unit (
 
 always @ (*) begin
   case (op)
-    SHIFT_OP_SLL: result <= a << b;   // SLL
-    SHIFT_OP_SRL: result <= a >> b;   // SRL
-    SHIFT_OP_SRA: result <= a >>> b;  // SRA
-    default:      result <= 32'b0;
+    SHIFT_OP_SLL: result = a << b;   // SLL
+    SHIFT_OP_SRL: result = a >> b;   // SRL
+    SHIFT_OP_SRA: result = a >>> b;  // SRA
+    default:      result = 32'b0;
   endcase
 end