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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 07:43:50 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 07:43:50 +0200 |
| commit | 0823d543685d2b1a49f99fff71852f8f74ed01c3 (patch) | |
| tree | 6bd0c9695b7590c908acf689532295daf1c756a0 | |
| parent | 9f1ab1f834c58c231617f3be12f16793061d4630 (diff) | |
| download | riscv_cpu-0823d543685d2b1a49f99fff71852f8f74ed01c3.tar.gz riscv_cpu-0823d543685d2b1a49f99fff71852f8f74ed01c3.zip | |
rv32 documentation
| -rw-r--r-- | README.md | 12 | ||||
| -rw-r--r-- | res/riscv_isa_registers_table.jpg | bin | 0 -> 117393 bytes | |||
| -rw-r--r-- | res/riscv_isa_rv32i_table.jpg | bin | 0 -> 339144 bytes |
3 files changed, 11 insertions, 1 deletions
@@ -62,7 +62,7 @@ The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardw ## Design -### Microarchitecture (RISC-V multicycle rv32i without ECALL/EBREAK) +### Microarchitecture (RISC-V multicycle rv32i without FENCE/ECALL/EBREAK)  @@ -85,3 +85,13 @@ Here we can see the waveforms of various internal signal of the CPU, executing t ```  + +## RISC-V + +### RV32I ISA + + + +### Registers + + diff --git a/res/riscv_isa_registers_table.jpg b/res/riscv_isa_registers_table.jpg Binary files differnew file mode 100644 index 0000000..99c00f4 --- /dev/null +++ b/res/riscv_isa_registers_table.jpg diff --git a/res/riscv_isa_rv32i_table.jpg b/res/riscv_isa_rv32i_table.jpg Binary files differnew file mode 100644 index 0000000..f4bc6db --- /dev/null +++ b/res/riscv_isa_rv32i_table.jpg |
