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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 17:23:14 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 17:23:14 +0200 |
| commit | 14e5e2120e1176ce63f73adddd102934144c0f12 (patch) | |
| tree | 17458628563c49120e9369eeb1267184f247c8c5 | |
| parent | 55b8324987d6253bfd70f069bff804b359e79cf5 (diff) | |
| download | riscv_cpu-14e5e2120e1176ce63f73adddd102934144c0f12.tar.gz riscv_cpu-14e5e2120e1176ce63f73adddd102934144c0f12.zip | |
updated README.md for new Makefile
| -rw-r--r-- | README.md | 7 |
1 files changed, 3 insertions, 4 deletions
@@ -4,10 +4,9 @@ An attempt at building a simple RISCV CPU in verilog. ## Build -* `make all` to synthesize, place and route the design and to generate the bitstream. +* `make all` alias for `make simulate`. +* `make simulate` to run all the testbenches (sim/testbench_*.v). +* `make bitstream` to synthesize, place and route the design and to generate the bitstream. * `make program` to upload the bitstream to the FPGA. * `make flash` to flash the bitsream to the FPGA. -* `make tests` to generate testvec files -* `make simulate` to run the testbench (sim/testbench.v). -* `make wave` to view the simulation in GTKWave. * `make clean` to clean build files. |