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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 07:46:21 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 07:46:21 +0200
commit4a52f5f4699a445c034300c5d292b6e919b924b0 (patch)
treed905f1fdb50fb26f91a569f9575f9fc9ab344919
parent0823d543685d2b1a49f99fff71852f8f74ed01c3 (diff)
downloadriscv_cpu-4a52f5f4699a445c034300c5d292b6e919b924b0.tar.gz
riscv_cpu-4a52f5f4699a445c034300c5d292b6e919b924b0.zip
mixed up riscv tables in README
-rw-r--r--README.md4
1 files changed, 2 insertions, 2 deletions
diff --git a/README.md b/README.md
index 96a7d4b..d98e570 100644
--- a/README.md
+++ b/README.md
@@ -90,8 +90,8 @@ Here we can see the waveforms of various internal signal of the CPU, executing t
### RV32I ISA
-![RV32I ISA Table](res/riscv_isa_registers_table.jpg)
+![RV32I ISA Table](res/riscv_isa_rv32i_table.jpg)
### Registers
-![RV32 Register Table](res/riscv_isa_rv32i_table.jpg)
+![RV32 Register Table](res/riscv_isa_registers_table.jpg)