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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:57:36 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:57:36 +0200 |
| commit | 5d41601bb83859e684d28c6c6cdf093851722604 (patch) | |
| tree | 5ee044c572827a9a8aab12799c8e68f06838b507 | |
| parent | 2a3951a25ffe28342177e29cf97125ed89ca59a4 (diff) | |
| download | riscv_cpu-5d41601bb83859e684d28c6c6cdf093851722604.tar.gz riscv_cpu-5d41601bb83859e684d28c6c6cdf093851722604.zip | |
fixed unsigned not recognized in verilog 2000 bug
| -rw-r--r-- | src/shift_unit.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v index eb931e2..1f2c96b 100644 --- a/src/shift_unit.v +++ b/src/shift_unit.v @@ -2,7 +2,7 @@ module shift_unit #( parameter N = 32 )( input signed [N-1:0] A, - input unsigned [N-1:0] SHAMT, + input [N-1:0] SHAMT, input [1:0] OP, // 00: SLL, 01: SRL, 11: SRA output reg [N-1:0] RESULT ); |