async reset

8 files changed, 10 insertions, 10 deletions

diff --git a/README.md b/README.md
index 68ac156..b65fea9 100644
--- a/README.md
+++ b/README.md
@@ -45,7 +45,7 @@ The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardw
 ## Currently Supported Instructions
 
 * R-type: add, sub, and, or, xor, sll, srl, sra, slt, sltu
-* I-type: addi, andi, ori, xori, slti, sltiu, slli, srli, srai
+* I-type: addi, andi, ori, xori, slti, sltiu, slli, srli, srai, lw
 * S-type: sw
 * B-type: beq, bne, blt, bge, bltu, bgeu
 * U-type:
diff --git a/src/alu_result_reg.v b/src/alu_result_reg.v
index 8de7a08..cece9e4 100644
--- a/src/alu_result_reg.v
+++ b/src/alu_result_reg.v
@@ -1,12 +1,12 @@
 module alu_result_reg (
   input clk, 
   input rstn,
-  
+
   input [31:0] alu_result_in,
   output reg [31:0] alu_result_buf
 );
 
-always @ (posedge clk) begin
+always @ (posedge clk or negedge rstn) begin
   if (!rstn) alu_result_buf <= 32'b0;
   else alu_result_buf <= alu_result_in;
 end
diff --git a/src/clock_divider.v b/src/clock_divider.v
index 0ece86d..a63e943 100644
--- a/src/clock_divider.v
+++ b/src/clock_divider.v
@@ -9,7 +9,7 @@ module clock_divider #(
 
 reg [31:0] counter = 0;
 
-always @(posedge clk) begin
+always @(posedge clk or negedge rstn) begin
   if (!rstn) begin
     counter <= 0;
     clk_div <= 0;
diff --git a/src/control_unit.v b/src/control_unit.v
index 9431c25..0565d5e 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -72,7 +72,7 @@ end
 
 reg [3:0] state, next_state;
 
-always @ (posedge clk) begin
+always @ (posedge clk or negedge rstn) begin
   if (!rstn) state <= s00_fetch;
   else state <= next_state;
 end
diff --git a/src/data_reg.v b/src/data_reg.v
index a32a9cf..473d50a 100644
--- a/src/data_reg.v
+++ b/src/data_reg.v
@@ -1,12 +1,12 @@
 module data_reg (
   input clk,
   input rstn,
-  
+
   input [31:0] data_in,
   output reg [31:0] data_buf
 );
 
-always @ (posedge clk) begin
+always @ (posedge clk or negedge rstn) begin
   if (!rstn) data_buf <= 32'b0;
   else data_buf <= data_in;
 end
diff --git a/src/instruction_reg.v b/src/instruction_reg.v
index 3c81cf6..d98ab6d 100644
--- a/src/instruction_reg.v
+++ b/src/instruction_reg.v
@@ -7,7 +7,7 @@ module instruction_reg (
   output reg [31:0] pc_buf, instr
 );
 
-always @ (posedge clk) begin
+always @ (posedge clk or negedge rstn) begin
   if (!rstn) begin
     pc_buf <= 32'b0;
     instr  <= 32'b0;
diff --git a/src/pc_reg.v b/src/pc_reg.v
index 91bf85f..2bdb540 100644
--- a/src/pc_reg.v
+++ b/src/pc_reg.v
@@ -10,7 +10,7 @@ module pc_reg (
 
 parameter PC_INITIAL = 32'h0001_0000;
 
-always @ (posedge clk) begin
+always @ (posedge clk or negedge rstn) begin
   if (!rstn) pc <= PC_INITIAL;
   else if (we) pc <= pc_in;
 end
diff --git a/src/register_file_reg.v b/src/register_file_reg.v
index 20222d7..b1bd4fc 100644
--- a/src/register_file_reg.v
+++ b/src/register_file_reg.v
@@ -9,7 +9,7 @@ module register_file_reg (
   output reg [31:0] rd2_buf
 );
 
-always @ (posedge clk) begin
+always @ (posedge clk or negedge rstn) begin
   if (!rstn) begin
     rd1_buf <= 32'b0;
     rd2_buf <= 32'b0;