added memory unit

5 files changed, 115 insertions, 13 deletions

diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v
index 093a624..07fa3e0 100644
--- a/sim/testbench_register_file.v
+++ b/sim/testbench_register_file.v
@@ -14,12 +14,12 @@ register_file uut (
   .clk(clk),
   .rst(rst),
   .we(we),
-  .addr_rs0(addr_rs0),
-  .addr_rs1(addr_rs1),
-  .addr_rd2(addr_rd2),
-  .data_rs0(data_rs0),
-  .data_rs1(data_rs1),
-  .data_rd2(data_rd2)
+  .addr_read0(addr_rs0),
+  .addr_read1(addr_rs1),
+  .addr_write2(addr_rd2),
+  .data_read0(data_rs0),
+  .data_read1(data_rs1),
+  .data_write2(data_rd2)
 );
 
 integer file, r, eof;
diff --git a/src/memory_unit.v b/src/memory_unit.v
new file mode 100644
index 0000000..7eb435b
--- /dev/null
+++ b/src/memory_unit.v
@@ -0,0 +1,58 @@
+module memory_unit #(
+  parameter N = 32
+)(
+  input clk,
+  input rst,
+  input we,
+  input [N-1:0] addr,
+  output reg [N-1:0] data_read,
+  input [N-1:0] data_write
+);
+
+reg we_ram;
+wire [N-1:0] data_read_ram, data_read_rom;
+
+ram #(.N(N), .SIZE(1024)) ram(
+  .clk(clk),
+  .rst(rst),
+  .we(we_ram),
+  .addr(addr[N-17:0]),
+  .data_read(data_read_ram),
+  .data_write(data_write)
+);
+
+rom #(.N(N), .SIZE(1024)) rom(
+  .clk(clk),
+  .rst(rst),
+  .addr(addr[N-17:0]),
+  .data_read(data_read_rom)
+);
+
+// 0000 0000 Reserved
+// 0000 FFFF
+//
+// 0001 0000 ROM
+// 000F FFFF
+//
+// 0010 0000 RAM
+// FF0F FFFF
+//
+// FF10 0000 Reserved
+// FFFF FFFF
+
+
+always @(*) begin
+  we_ram = 0;
+  if (addr[N-1:N-16] == 16'h0000) begin
+    data_read <= 0;
+  end else if (addr[N-1:N-16] >= 16'h0001 && addr[N-1:N-16] <= 16'h000F) begin
+    data_read <= data_read_rom;
+    we_ram = we;
+  end else if (addr[N-1:N-16] >= 16'h0010 && addr[N-1:N-16] <= 16'hFF0F) begin
+    data_read <= data_read_ram;
+  end else if (addr[N-1:N-16] >= 16'hFF10 && addr[N-1:N-16] <= 16'hFFFF) begin
+    data_read <= 0;
+  end
+end
+
+endmodule
diff --git a/src/ram.v b/src/ram.v
new file mode 100644
index 0000000..b7e4c80
--- /dev/null
+++ b/src/ram.v
@@ -0,0 +1,31 @@
+module ram #(
+  parameter N = 32, 
+  parameter SIZE = 1024
+)(
+    input clk,
+    input rst,
+    input we,
+    input [log2(SIZE)-1:0] addr,
+    input [N-1:0] data_write,
+    output reg [N-1:0] data_read
+);
+
+`include "include/log2.vh"
+
+reg [8:0] ram_block [SIZE-1:0];
+
+integer i;
+always @(posedge clk or posedge rst) begin
+  if (rst) begin
+    for (i = 0; i < SIZE; i = i + 1)
+      ram_block[i] <= 0;
+  end else begin
+    if (we) begin
+      ram_block[addr] = data_write;
+    end
+    data_read = ram_block[addr];      
+  end
+
+end
+
+endmodule
diff --git a/src/register_file.v b/src/register_file.v
index 4846be8..de697ab 100644
--- a/src/register_file.v
+++ b/src/register_file.v
@@ -3,9 +3,9 @@ module register_file #(
   parameter XLEN = 32
 )(
   input clk, rst, we,
-  input [log2(N)-1:0] addr_rs0, addr_rs1, addr_rd2,
-  input [N-1:0] data_rd2,
-  output reg [N-1:0] data_rs0, data_rs1
+  input [log2(XLEN)-1:0] addr_read0, addr_read1, addr_write2,
+  input [N-1:0] data_write2,
+  output reg [N-1:0] data_read0, data_read1
 );
 
 `include "include/log2.vh"
@@ -18,10 +18,10 @@ always @(posedge clk or rst) begin
     for (i = 1; i < XLEN; i = i + 1)
       registers[i] <= 0;
   end else begin
-    data_rs0 = (addr_rs0 == 0) ? 0 : registers[addr_rs0];
-    data_rs1 = (addr_rs1 == 0) ? 0 : registers[addr_rs1];
-    if (we && (addr_rd2 != 0)) begin
-      registers[addr_rd2] = data_rd2;
+    data_read0 = (addr_read0 == 0) ? 0 : registers[addr_read0];
+    data_read1 = (addr_read1 == 0) ? 0 : registers[addr_read1];
+    if (we && (addr_write2 != 0)) begin
+      registers[addr_write2] <= data_write2;
     end
   end
 end
diff --git a/src/rom.v b/src/rom.v
new file mode 100644
index 0000000..90a9846
--- /dev/null
+++ b/src/rom.v
@@ -0,0 +1,13 @@
+module rom #(
+  parameter N = 32, 
+  parameter SIZE = 1024
+)(
+    input clk,
+    input rst,
+    input [log2(SIZE)-1:0] addr,
+    output [N-1:0] data_read
+);
+
+`include "include/log2.vh"
+
+endmodule