refactoring constants

12 files changed, 198 insertions, 106 deletions

diff --git a/include/consts.vh b/include/consts.vh
new file mode 100644
index 0000000..49133a7
--- /dev/null
+++ b/include/consts.vh
@@ -0,0 +1,108 @@
+parameter ALU_A_SRC_PC      = 2'b00;
+parameter ALU_A_SRC_PC_BUF  = 2'b01;
+parameter ALU_A_SRC_RD1_BUF = 2'b10;
+parameter ALU_A_SRC_0       = 2'b11;
+
+parameter ALU_B_SRC_RD2_BUF = 2'b00;
+parameter ALU_B_SRC_IMM     = 2'b01;
+parameter ALU_B_SRC_4       = 2'b10;
+
+parameter RESULT_SRC_ALU_RESULT_BUF = 2'b00;
+parameter RESULT_SRC_DATA_BUF       = 2'b01;
+parameter RESULT_SRC_ALU_RESULT     = 2'b10;
+
+parameter MEM_ADDR_SRC_PC     = 1'b0;
+parameter MEM_ADDR_SRC_RESULT = 1'b1;
+
+parameter ARITHMETIC_OP_ADD  = 2'b00;
+parameter ARITHMETIC_OP_SUB  = 2'b01;
+parameter ARITHMETIC_OP_SLT  = 2'b10;
+parameter ARITHMETIC_OP_SLTU = 2'b11;
+
+parameter LOGIC_OP_AND = 2'b00;
+parameter LOGIC_OP_OR  = 2'b01;
+parameter LOGIC_OP_XOR = 2'b10;
+
+parameter SHIFT_OP_SLL = 2'b00;
+parameter SHIFT_OP_SRL = 2'b01;
+parameter SHIFT_OP_SRA = 2'b11;
+
+parameter ALU_OP_ARITHMETIC = 2'b00;
+parameter ALU_OP_LOGIC      = 2'b01;
+parameter ALU_OP_SHIFT      = 2'b10;
+
+parameter ALU_OP_ADD  = { ALU_OP_ARITHMETIC, ARITHMETIC_OP_ADD };
+parameter ALU_OP_SUB  = { ALU_OP_ARITHMETIC, ARITHMETIC_OP_SUB };
+parameter ALU_OP_SLT  = { ALU_OP_ARITHMETIC, ARITHMETIC_OP_SLT };
+parameter ALU_OP_SLTU = { ALU_OP_ARITHMETIC, ARITHMETIC_OP_SLTU };
+parameter ALU_OP_AND  = { ALU_OP_LOGIC, LOGIC_OP_AND };
+parameter ALU_OP_OR   = { ALU_OP_LOGIC, LOGIC_OP_OR };
+parameter ALU_OP_XOR  = { ALU_OP_LOGIC, LOGIC_OP_XOR };
+parameter ALU_OP_SLL  = { ALU_OP_SHIFT, SHIFT_OP_SLL };
+parameter ALU_OP_SRL  = { ALU_OP_SHIFT, SHIFT_OP_SRL };
+parameter ALU_OP_SRA  = { ALU_OP_SHIFT, SHIFT_OP_SRA };
+
+parameter STATE_FETCH     = 4'h0;
+parameter STATE_DECODE    = 4'h1;
+parameter STATE_MEM_ADDR  = 4'h2;
+parameter STATE_MEM_LOAD  = 4'h3;
+parameter STATE_MEM_STORE = 4'h4;
+parameter STATE_MEM_WB    = 4'h5;
+parameter STATE_EXECUTE_R = 4'h6;
+parameter STATE_EXECUTE_I = 4'h7;
+parameter STATE_JAL       = 4'h8;
+parameter STATE_JALR      = 4'h9;
+parameter STATE_LUI       = 4'ha;
+parameter STATE_ALU_WB    = 4'hb;
+parameter STATE_AUIPC     = 4'hc;
+parameter STATE_BRANCH    = 4'hd;
+
+parameter INSTR_FORMAT_UNKNOWN = 3'b000;
+parameter INSTR_FORMAT_R       = 3'b001;
+parameter INSTR_FORMAT_I       = 3'b010;
+parameter INSTR_FORMAT_S       = 3'b011;
+parameter INSTR_FORMAT_B       = 3'b100;
+parameter INSTR_FORMAT_U       = 3'b101;
+parameter INSTR_FORMAT_J       = 3'b110;
+
+parameter OPCODE_LUI    = 7'b0110111;
+parameter OPCODE_AUIPC  = 7'b0010111;
+parameter OPCODE_JAL    = 7'b1101111;
+parameter OPCODE_JALR   = 7'b1100111;
+parameter OPCODE_BRANCH = 7'b1100011;
+parameter OPCODE_LOAD   = 7'b0000011;
+parameter OPCODE_STORE  = 7'b0100011;
+parameter OPCODE_IMM    = 7'b0010011;
+parameter OPCODE_REG    = 7'b0110011;
+parameter OPCODE_SYNC   = 7'b0001111;
+parameter OPCODE_SYS    = 7'b1110011;
+
+parameter FUNCT3_LS_B  = 3'b000;
+parameter FUNCT3_LS_H  = 3'b001;
+parameter FUNCT3_LS_W  = 3'b010;
+parameter FUNCT3_LS_BU = 3'b100;
+parameter FUNCT3_LS_HU = 3'b101;
+
+parameter FUNCT3_ALU_ADD_SUB = 3'b000;
+parameter FUNCT3_ALU_SLT     = 3'b010;
+parameter FUNCT3_ALU_SLTU    = 3'b011;
+parameter FUNCT3_ALU_XOR     = 3'b100;
+parameter FUNCT3_ALU_OR      = 3'b110;
+parameter FUNCT3_ALU_AND     = 3'b111;
+parameter FUNCT3_ALU_SLL     = 3'b001;
+parameter FUNCT3_ALU_SR      = 3'b101;
+
+parameter FUNCT3_BRANCH_BEQ  = 3'b000;
+parameter FUNCT3_BRANCH_BNE  = 3'b001;
+parameter FUNCT3_BRANCH_BLT  = 3'b100;
+parameter FUNCT3_BRANCH_BGE  = 3'b101;
+parameter FUNCT3_BRANCH_BLTU = 3'b110;
+parameter FUNCT3_BRANCH_BGEU = 3'b111;
+
+parameter FUNCT7_ALU_ADD = 7'b0000000;
+parameter FUNCT7_ALU_SUB = 7'b0100000;
+parameter FUNCT7_ALU_SRL = 7'b0000000;
+parameter FUNCT7_ALU_SRA = 7'b0100000;
+
+parameter ALU_CTRL_OP  = 1'b0;
+parameter ALU_CTRL_ADD = 1'b1;
\ No newline at end of file
diff --git a/src/alu.v b/src/alu.v
index b7c5b07..839128e 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -31,12 +31,14 @@ shift_unit su (
   .result(shift_result)
 );
 
+`include "include/consts.vh"
+
 always @ (*) begin
   case (op[3:2])
-    2'b00: result <= arithmetic_result; // ARITHMETIC
-    2'b01: result <= logic_result;      // LOGIC
-    2'b10: result <= shift_result;      // SHIFT
-    default: result <= 31'b0;
+    ALU_OP_ARITHMETIC: result <= arithmetic_result; // ARITHMETIC
+    ALU_OP_LOGIC:      result <= logic_result;      // LOGIC
+    ALU_OP_SHIFT:      result <= shift_result;      // SHIFT
+    default:           result <= 31'b0;
   endcase
 end
 
diff --git a/src/alu_a_src_mux.v b/src/alu_a_src_mux.v
index b51dd5b..208cc82 100644
--- a/src/alu_a_src_mux.v
+++ b/src/alu_a_src_mux.v
@@ -8,12 +8,15 @@ module alu_a_src_mux (
   output reg [31:0] alu_a
 );
 
+`include "include/consts.vh"
+
 always @(*) begin
   case (alu_a_src)
-    2'b00:   alu_a <= src_pc;
-    2'b01:   alu_a <= src_pc_buf;
-    2'b10:   alu_a <= src_rd1_buf;
-    default: alu_a <= 32'b0;
+    ALU_A_SRC_PC:      alu_a <= src_pc;
+    ALU_A_SRC_PC_BUF:  alu_a <= src_pc_buf;
+    ALU_A_SRC_RD1_BUF: alu_a <= src_rd1_buf;
+    ALU_A_SRC_0:       alu_a <= 32'b0;
+    default:           alu_a <= 32'b0;
   endcase
 end
 
diff --git a/src/alu_b_src_mux.v b/src/alu_b_src_mux.v
index 99dffab..615d312 100644
--- a/src/alu_b_src_mux.v
+++ b/src/alu_b_src_mux.v
@@ -7,12 +7,14 @@ module alu_b_src_mux (
   output reg [31:0] alu_b
 );
 
+`include "include/consts.vh"
+
 always @(*) begin
   case (alu_b_src)
-    2'b00:   alu_b <= src_rd2_buf;
-    2'b01:   alu_b <= src_imm;
-    2'b10:   alu_b <= 32'h4;
-    default: alu_b <= 32'b0;
+    ALU_B_SRC_RD2_BUF: alu_b <= src_rd2_buf;
+    ALU_B_SRC_IMM:     alu_b <= src_imm;
+    ALU_B_SRC_4:       alu_b <= 32'h4;
+    default:           alu_b <= 32'b0;
   endcase
 end
 
diff --git a/src/alu_op_decode.v b/src/alu_op_decode.v
index 4a812ab..0e217ec 100644
--- a/src/alu_op_decode.v
+++ b/src/alu_op_decode.v
@@ -8,79 +8,36 @@ module alu_op_decode (
   output reg [3:0] alu_op
 );
 
-parameter ALU_OP_ADD  = 4'b0000,
-          ALU_OP_SUB  = 4'b0001,
-          ALU_OP_SLT  = 4'b0010,
-          ALU_OP_SLTU = 4'b0011,
-          ALU_OP_AND  = 4'b0100,
-          ALU_OP_OR   = 4'b0101,
-          ALU_OP_XOR  = 4'b0110,
-          ALU_OP_SLL  = 4'b1000,
-          ALU_OP_SRL  = 4'b1001,
-          ALU_OP_SRA  = 4'b1011;
-
+`include "include/consts.vh"
 
 always @ (*) begin
-  if (alu_ctrl == 1'b1) alu_op <= ALU_OP_ADD;
-  else case (opcode)
-    7'b0110011: begin // ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
-      case (funct3)
-        3'b000:  alu_op <= funct7[5] ? ALU_OP_SUB : ALU_OP_ADD;
-        3'b001:  alu_op <= ALU_OP_SLL;
-        3'b010:  alu_op <= ALU_OP_SLT;
-        3'b011:  alu_op <= ALU_OP_SLTU;
-        3'b100:  alu_op <= ALU_OP_XOR;
-        3'b101:  alu_op <= funct7[5] ? ALU_OP_SRA : ALU_OP_SRL;
-        3'b110:  alu_op <= ALU_OP_OR;
-        3'b111:  alu_op <= ALU_OP_AND;
-        default: alu_op <= ALU_OP_ADD;
-      endcase
-    end
-    7'b0010011: begin // ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
-      case (funct3)
-        3'b000:  alu_op <= ALU_OP_ADD;
-        3'b001:  alu_op <= ALU_OP_SLL;
-        3'b010:  alu_op <= ALU_OP_SLT;
-        3'b011:  alu_op <= ALU_OP_SLTU;
-        3'b100:  alu_op <= ALU_OP_XOR;
-        3'b101:  alu_op <= funct7[5] ? ALU_OP_SRA : ALU_OP_SRL;
-        3'b110:  alu_op <= ALU_OP_OR;
-        3'b111:  alu_op <= ALU_OP_AND;
-        default: alu_op <= ALU_OP_ADD;
-      endcase
-    end
-    7'b0000011: begin // LB, LH, LW, LBU, LHU
-      alu_op <= ALU_OP_ADD;
-    end
-    7'b1100111: begin // JALR
-      alu_op <= ALU_OP_ADD;
-    end
-    7'b0100011: begin // SB, SH, SW
-      alu_op <= ALU_OP_ADD;
-    end
-    7'b1100011: begin // BEQ, BNE, BLT, BGE, BLTU, BGEU
-      if ((funct3 == 3'b000) | (funct3 == 3'b001)) alu_op <= ALU_OP_SUB;
-      else if ((funct3 == 3'b100) | (funct3 == 3'b101)) alu_op <= ALU_OP_SLT;
-      else if ((funct3 == 3'b110) | (funct3 == 3'b111)) alu_op <= ALU_OP_SLTU; 
-      else alu_op <= ALU_OP_ADD;
-    end
-    7'b0110111: begin // LUI
-      alu_op <= ALU_OP_ADD;
-    end
-    7'b0010111: begin // AUIPC
-      alu_op <= ALU_OP_ADD;
-    end
-    7'b1101111: begin // JAL
-      alu_op <= ALU_OP_ADD;
-    end
-    7'b0001111: begin // FENCE, FENCE.I
-      alu_op <= ALU_OP_ADD;
-    end
-    7'b1110011: begin // ECALL, EBREAK, CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI
-      alu_op <= ALU_OP_ADD;
-    end
-    default: alu_op <= ALU_OP_ADD;
-  endcase
+  if (alu_ctrl == ALU_CTRL_ADD) begin
+    alu_op <= ALU_OP_ADD;
+  end else if (opcode == OPCODE_REG || opcode == OPCODE_IMM) begin
+    case (funct3)
+      FUNCT3_ALU_ADD_SUB: alu_op <= (opcode == OPCODE_REG || funct7 == FUNCT7_ALU_SUB) ? ALU_OP_SUB : ALU_OP_ADD;
+      FUNCT3_ALU_SLL:     alu_op <= ALU_OP_SLL;
+      FUNCT3_ALU_SLT:     alu_op <= ALU_OP_SLT;
+      FUNCT3_ALU_SLTU:    alu_op <= ALU_OP_SLTU;
+      FUNCT3_ALU_XOR:     alu_op <= ALU_OP_XOR;
+      FUNCT3_ALU_SR:      alu_op <= funct7 == FUNCT7_ALU_SRL ? ALU_OP_SRL : ALU_OP_SRA;
+      FUNCT3_ALU_OR:      alu_op <= ALU_OP_OR;
+      FUNCT3_ALU_AND:     alu_op <= ALU_OP_AND;
+      default:            alu_op <= ALU_OP_ADD;
+    endcase
+  end else if (opcode == OPCODE_BRANCH) begin
+    case (funct3)
+      FUNCT3_BRANCH_BEQ:  alu_op <= ALU_OP_SUB;
+      FUNCT3_BRANCH_BNE:  alu_op <= ALU_OP_SUB;
+      FUNCT3_BRANCH_BLT:  alu_op <= ALU_OP_SLT;
+      FUNCT3_BRANCH_BGE:  alu_op <= ALU_OP_SLT;
+      FUNCT3_BRANCH_BLTU: alu_op <= ALU_OP_SLTU;
+      FUNCT3_BRANCH_BGEU: alu_op <= ALU_OP_SLTU;
+      default:            alu_op <= ALU_OP_ADD;
+    endcase
+  end else begin
+    alu_op <= ALU_OP_ADD;
+  end
 end
 
 endmodule
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v
index 261b526..2ac302e 100644
--- a/src/arithmetic_unit.v
+++ b/src/arithmetic_unit.v
@@ -7,6 +7,8 @@ module arithmetic_unit (
   output reg [31:0] result
 );
 
+`include "include/consts.vh"
+
 wire signed [31:0] a_signed, b_signed;
 
 assign a_signed = a;
@@ -14,10 +16,11 @@ assign b_signed = b;
 
 always @ (*) begin
   case (op)
-    2'b00: result <= a + b;                               // ADD
-    2'b01: result <= a - b;                               // SUB
-    2'b10: result <= { {31{1'b0}}, a_signed < b_signed }; // SLT
-    2'b11: result <= { {31{1'b0}}, a < b };               // SLTU
+    ARITHMETIC_OP_ADD:  result <= a + b;                               // ADD
+    ARITHMETIC_OP_SUB:  result <= a - b;                               // SUB
+    ARITHMETIC_OP_SLT:  result <= { {31{1'b0}}, a_signed < b_signed }; // SLT
+    ARITHMETIC_OP_SLTU: result <= { {31{1'b0}}, a < b };               // SLTU
+    default:            result <= 32'b0;
   endcase
 end
 
diff --git a/src/control_unit.v b/src/control_unit.v
index 0565d5e..494737e 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -14,6 +14,7 @@ module control_unit (
  output reg instr_we,
 
  output reg rf_we,
+ output [4:0] ra1, ra2, wa3,
 
  output reg [1:0] alu_a_src,
  output reg [1:0] alu_b_src,
@@ -52,6 +53,10 @@ assign opcode = instr[6:0];
 assign funct3 = instr[14:12];
 assign funct7 = instr[31:25];
 
+assign ra1 = instr[19:15];
+assign ra2 = instr[24:20];
+assign wa3 = instr[11:7];
+
 
 always @ (*) begin
   case (opcode)
diff --git a/src/cpu.v b/src/cpu.v
index bab556b..879e8f8 100644
--- a/src/cpu.v
+++ b/src/cpu.v
@@ -19,7 +19,10 @@ control_unit control_unit (
   .alu_op(alu_op),
   .alu_a_src(alu_a_src),
   .alu_b_src(alu_b_src),
-  .rf_we(rf_we)
+  .rf_we(rf_we),
+  .ra1(ra1),
+  .ra2(ra2),
+  .wa3(wa3)
 );
 
 
@@ -40,6 +43,7 @@ wire [2:0] imm_src;
 wire [31:0] data_buf;
 
 wire rf_we;
+wire [4:0] ra1, ra2, wa3;
 wire [31:0] rd1, rd2;
 wire [31:0] rd1_buf, rd2_buf;
 
@@ -106,9 +110,9 @@ register_file register_file (
   .clk(clk),
   .rstn(rstn),
   .we(rf_we),
-  .ra1(instr[19:15]),
-  .ra2(instr[24:20]),
-  .wa3(instr[11:7]),
+  .ra1(ra1),
+  .ra2(ra2),
+  .wa3(wa3),
   .rd1(rd1),
   .rd2(rd2),
   .wd3(result),
diff --git a/src/logic_unit.v b/src/logic_unit.v
index c717f23..ca858d0 100644
--- a/src/logic_unit.v
+++ b/src/logic_unit.v
@@ -6,13 +6,15 @@ module logic_unit (
   
   output reg [31:0] result
 );
+
+`include "include/consts.vh"
   
 always @ (*) begin
   case (op)
-    2'b00: result <= a & b; // AND
-    2'b01: result <= a | b; // OR
-    2'b10: result <= a ^ b; // XOR
-    default: result <= 32'b0;
+    LOGIC_OP_AND: result <= a & b; // AND
+    LOGIC_OP_OR:  result <= a | b; // OR
+    LOGIC_OP_XOR: result <= a ^ b; // XOR
+    default:      result <= 32'b0;
   endcase
 end
 
diff --git a/src/mem_addr_src_mux.v b/src/mem_addr_src_mux.v
index c5c64f0..633b345 100644
--- a/src/mem_addr_src_mux.v
+++ b/src/mem_addr_src_mux.v
@@ -7,11 +7,13 @@ module mem_addr_src_mux (
   output reg [31:0] mem_addr
 );
 
+`include "include/consts.vh"
+
 always @(*) begin
   case (mem_addr_src)
-    1'b0:    mem_addr <= src_pc;
-    1'b1:    mem_addr <= src_result;
-    default: mem_addr <= 32'b0;
+    MEM_ADDR_SRC_PC:     mem_addr <= src_pc;
+    MEM_ADDR_SRC_RESULT: mem_addr <= src_result;
+    default:             mem_addr <= 32'b0;
   endcase
 end
 
diff --git a/src/result_mux.v b/src/result_mux.v
index 047a392..528913d 100644
--- a/src/result_mux.v
+++ b/src/result_mux.v
@@ -8,12 +8,14 @@ module result_mux (
   output reg [31:0] result
 );
 
+`include "include/consts.vh"
+
 always @(*) begin
   case (result_src)
-    2'b00:   result <= src_alu_result_buf;
-    2'b01:   result <= src_data_buf;
-    2'b10:   result <= src_alu_result;
-    default: result <= 32'b0;
+    RESULT_SRC_ALU_RESULT_BUF: result <= src_alu_result_buf;
+    RESULT_SRC_DATA_BUF:       result <= src_data_buf;
+    RESULT_SRC_ALU_RESULT:     result <= src_alu_result;
+    default:                   result <= 32'b0;
   endcase
 end
 
diff --git a/src/shift_unit.v b/src/shift_unit.v
index ae1d665..e92334d 100644
--- a/src/shift_unit.v
+++ b/src/shift_unit.v
@@ -7,12 +7,14 @@ module shift_unit (
   output reg [31:0] result
 );
 
+`include "include/consts.vh"
+
 always @ (*) begin
   case (op)
-    2'b00: result <= a << b;   // SLL
-    2'b01: result <= a >> b;   // SRL
-    2'b11: result <= a >>> b;  // SRA
-    default: result <= 32'b0;
+    SHIFT_OP_SLL: result <= a << b;   // SLL
+    SHIFT_OP_SRL: result <= a >> b;   // SRL
+    SHIFT_OP_SRA: result <= a >>> b;  // SRA
+    default:      result <= 32'b0;
   endcase
 end