| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-05-21 | restructured project | Flavian Kaufmann | |
| 2024-05-14 | bug fixes | Flavian Kaufmann | |
| 2024-05-13 | refactoring constants | Flavian Kaufmann | |
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann | |
| 2024-05-07 | cpu | Flavian Kaufmann | |
| 2024-05-05 | added register file | Flavian Kaufmann | |
| 2024-05-04 | renamed some signals | Flavian Kaufmann | |
| 2024-05-01 | fixed unsigned not recognized in verilog 2000 bug | Flavian Kaufmann | |
| 2024-05-01 | fixed alu bugs | Flavian Kaufmann | |
| 2024-05-01 | alu | Flavian Kaufmann | |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
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