diff options
| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
| commit | 9d69eaa8e3be69ead0918d915bdacb7d0def9281 (patch) | |
| tree | ba08ada6f1a0ca95ace1311d176f265139ac95b9 /src/shift_unit.v | |
| parent | f2e07b4ae7f4410efaf100e830a51d7dcb0d1b28 (diff) | |
| download | riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.tar.gz riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.zip | |
cpu
Diffstat (limited to 'src/shift_unit.v')
| -rw-r--r-- | src/shift_unit.v | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v index d0aa9d3..df4b01d 100644 --- a/src/shift_unit.v +++ b/src/shift_unit.v @@ -1,17 +1,16 @@ -module shift_unit #( - parameter N = 32 -)( - input signed [N-1:0] src0, - input [N-1:0] shamt, - input [1:0] op, // 00: SLL, 01: SRL, 11: SRA - output reg [N-1:0] result +module shift_unit ( + input signed [31:0] a, + input [4:0] b, + input [1:0] op, + output reg [31:0] result ); always @ (*) begin case (op) - 2'b00: result <= src0 << shamt % N; - 2'b01: result <= src0 >> shamt % N; - 2'b11: result <= src0 >>> shamt % N; + 2'b00: result <= a << b; // SLL + 2'b01: result <= a >> b; // SRL + 2'b11: result <= a >>> b; // SRA + default: result <= 32'b0; endcase end |