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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-05 10:27:21 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-05 10:27:21 +0200 |
| commit | 8d5d730269cc94fa8d5caed0e1996e3d94be25d1 (patch) | |
| tree | 73154eacc2c7483a24aecd05a984638ff322d5d6 /src/shift_unit.v | |
| parent | f6a55d5faba42120aa900e2514d9ff5d80dfca8b (diff) | |
| download | riscv_cpu-8d5d730269cc94fa8d5caed0e1996e3d94be25d1.tar.gz riscv_cpu-8d5d730269cc94fa8d5caed0e1996e3d94be25d1.zip | |
added register file
Diffstat (limited to 'src/shift_unit.v')
| -rw-r--r-- | src/shift_unit.v | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v index 372fec0..d0aa9d3 100644 --- a/src/shift_unit.v +++ b/src/shift_unit.v @@ -1,17 +1,17 @@ module shift_unit #( parameter N = 32 )( - input signed [N-1:0] su_src0, - input [N-1:0] su_shamt, - input [1:0] su_op, // 00: SLL, 01: SRL, 11: SRA - output reg [N-1:0] su_result + input signed [N-1:0] src0, + input [N-1:0] shamt, + input [1:0] op, // 00: SLL, 01: SRL, 11: SRA + output reg [N-1:0] result ); always @ (*) begin - case (su_op) - 2'b00: su_result <= su_src0 << su_shamt % N; - 2'b01: su_result <= su_src0 >> su_shamt % N; - 2'b11: su_result <= su_src0 >>> su_shamt % N; + case (op) + 2'b00: result <= src0 << shamt % N; + 2'b01: result <= src0 >> shamt % N; + 2'b11: result <= src0 >>> shamt % N; endcase end |