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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-14 10:38:47 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-14 10:38:47 +0200 |
| commit | d107f7e40f02a7374b8685ba310500a6c38d43b1 (patch) | |
| tree | 55615eaface31b2473be3dae90fe822c5373f492 /src/shift_unit.v | |
| parent | 48b36fddef862c3cd5efbdd3ed3e86b179ac117b (diff) | |
| download | riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.tar.gz riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.zip | |
bug fixes
Diffstat (limited to 'src/shift_unit.v')
| -rw-r--r-- | src/shift_unit.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v index e92334d..ea83e4a 100644 --- a/src/shift_unit.v +++ b/src/shift_unit.v @@ -11,10 +11,10 @@ module shift_unit ( always @ (*) begin case (op) - SHIFT_OP_SLL: result <= a << b; // SLL - SHIFT_OP_SRL: result <= a >> b; // SRL - SHIFT_OP_SRA: result <= a >>> b; // SRA - default: result <= 32'b0; + SHIFT_OP_SLL: result = a << b; // SLL + SHIFT_OP_SRL: result = a >> b; // SRL + SHIFT_OP_SRA: result = a >>> b; // SRA + default: result = 32'b0; endcase end |