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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 12:40:49 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 12:40:49 +0200 |
| commit | 766273a6a50d57777e455d07a015300255becb6d (patch) | |
| tree | e283ed5c50a9c8af7d0624c0bc7440b0ccda0af9 /src/shift_unit.v | |
| parent | 1ee5fc13995ee1383b0b75a19003b08fe33cfa54 (diff) | |
| download | riscv_cpu-766273a6a50d57777e455d07a015300255becb6d.tar.gz riscv_cpu-766273a6a50d57777e455d07a015300255becb6d.zip | |
alu
Diffstat (limited to 'src/shift_unit.v')
| -rw-r--r-- | src/shift_unit.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v new file mode 100644 index 0000000..55b6add --- /dev/null +++ b/src/shift_unit.v @@ -0,0 +1,18 @@ +module shift_unit #( + parameter N = 32 +)( + input [N-1:0] A, + input [clog2(N):0] SHAMT, + input [1:0] OP, // 00: SLL, 01: SRL, 11: SRA + output reg [N-1:0] RESULT +); + +always @ (*) begin + case (OP) + 2'b00: RESULT <= A << SHAMT; + 2'b01: RESULT <= A >> SHAMT; + 2'b11: RESULT <= A >>> SHAMT; + endcase +end + +endmodule |