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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:08:53 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:08:53 +0200 |
| commit | ca5a25cfbdbefada9dfb94a097b65e69226f3f9a (patch) | |
| tree | cc9598ea41947b1e4cf008f430fc56e1c727d968 /src/shift_unit.v | |
| parent | 51b0a4c850fbf0ed70abe694be143b2b10e3e578 (diff) | |
| download | riscv_cpu-ca5a25cfbdbefada9dfb94a097b65e69226f3f9a.tar.gz riscv_cpu-ca5a25cfbdbefada9dfb94a097b65e69226f3f9a.zip | |
fixed alu bugs
Diffstat (limited to 'src/shift_unit.v')
| -rw-r--r-- | src/shift_unit.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v index 55b6add..eb931e2 100644 --- a/src/shift_unit.v +++ b/src/shift_unit.v @@ -1,17 +1,17 @@ module shift_unit #( parameter N = 32 )( - input [N-1:0] A, - input [clog2(N):0] SHAMT, + input signed [N-1:0] A, + input unsigned [N-1:0] SHAMT, input [1:0] OP, // 00: SLL, 01: SRL, 11: SRA output reg [N-1:0] RESULT ); always @ (*) begin case (OP) - 2'b00: RESULT <= A << SHAMT; - 2'b01: RESULT <= A >> SHAMT; - 2'b11: RESULT <= A >>> SHAMT; + 2'b00: RESULT <= A << SHAMT % N; + 2'b01: RESULT <= A >> SHAMT % N; + 2'b11: RESULT <= A >>> SHAMT % N; endcase end |