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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
| commit | 9c7d7fd782f70d99120ce6ac45a897606b52c878 (patch) | |
| tree | a6f36fed8ec3e42e08d51afee500190af8194df4 /src/shift_unit.v | |
| parent | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (diff) | |
| download | riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.tar.gz riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.zip | |
refactoring constants
Diffstat (limited to 'src/shift_unit.v')
| -rw-r--r-- | src/shift_unit.v | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v index ae1d665..e92334d 100644 --- a/src/shift_unit.v +++ b/src/shift_unit.v @@ -7,12 +7,14 @@ module shift_unit ( output reg [31:0] result ); +`include "include/consts.vh" + always @ (*) begin case (op) - 2'b00: result <= a << b; // SLL - 2'b01: result <= a >> b; // SRL - 2'b11: result <= a >>> b; // SRA - default: result <= 32'b0; + SHIFT_OP_SLL: result <= a << b; // SLL + SHIFT_OP_SRL: result <= a >> b; // SRL + SHIFT_OP_SRA: result <= a >>> b; // SRA + default: result <= 32'b0; endcase end |