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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
| commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
| tree | 91fa71b3960d1ad5217759371143efbdd833d475 /src/shift_unit.v | |
| parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
| download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip | |
restructured project
Diffstat (limited to 'src/shift_unit.v')
| -rw-r--r-- | src/shift_unit.v | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v deleted file mode 100644 index ea83e4a..0000000 --- a/src/shift_unit.v +++ /dev/null @@ -1,21 +0,0 @@ -module shift_unit ( - input signed [31:0] a, - input [4:0] b, - - input [1:0] op, - - output reg [31:0] result -); - -`include "include/consts.vh" - -always @ (*) begin - case (op) - SHIFT_OP_SLL: result = a << b; // SLL - SHIFT_OP_SRL: result = a >> b; // SRL - SHIFT_OP_SRA: result = a >>> b; // SRA - default: result = 32'b0; - endcase -end - -endmodule |