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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 18:30:51 +0200 |
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| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 18:30:51 +0200 |
| commit | f6a55d5faba42120aa900e2514d9ff5d80dfca8b (patch) | |
| tree | c03fd620359c72402876ddb4708663166599b390 /src/shift_unit.v | |
| parent | 14e5e2120e1176ce63f73adddd102934144c0f12 (diff) | |
| download | riscv_cpu-f6a55d5faba42120aa900e2514d9ff5d80dfca8b.tar.gz riscv_cpu-f6a55d5faba42120aa900e2514d9ff5d80dfca8b.zip | |
renamed some signals
Diffstat (limited to 'src/shift_unit.v')
| -rw-r--r-- | src/shift_unit.v | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/shift_unit.v b/src/shift_unit.v index 1f2c96b..372fec0 100644 --- a/src/shift_unit.v +++ b/src/shift_unit.v @@ -1,17 +1,17 @@ module shift_unit #( parameter N = 32 )( - input signed [N-1:0] A, - input [N-1:0] SHAMT, - input [1:0] OP, // 00: SLL, 01: SRL, 11: SRA - output reg [N-1:0] RESULT + input signed [N-1:0] su_src0, + input [N-1:0] su_shamt, + input [1:0] su_op, // 00: SLL, 01: SRL, 11: SRA + output reg [N-1:0] su_result ); always @ (*) begin - case (OP) - 2'b00: RESULT <= A << SHAMT % N; - 2'b01: RESULT <= A >> SHAMT % N; - 2'b11: RESULT <= A >>> SHAMT % N; + case (su_op) + 2'b00: su_result <= su_src0 << su_shamt % N; + 2'b01: su_result <= su_src0 >> su_shamt % N; + 2'b11: su_result <= su_src0 >>> su_shamt % N; endcase end |