| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-05 | register file testbench | Flavian Kaufmann |
| 2024-05-05 | added register file | Flavian Kaufmann |
| 2024-05-04 | renamed some signals | Flavian Kaufmann |
| 2024-05-04 | updated README.md for new Makefile | Flavian Kaufmann |
| 2024-05-04 | added support for multiple testbenches | Flavian Kaufmann |
| 2024-05-02 | register file | Flavian Kaufmann |
| 2024-05-02 | cleaned test output | Flavian Kaufmann |
| 2024-05-01 | fixed unsigned not recognized in verilog 2000 bug | Flavian Kaufmann |
| 2024-05-01 | added make target for testvec generation | Flavian Kaufmann |
| 2024-05-01 | read alu_testvec.txt from tests/ | Flavian Kaufmann |
| 2024-05-01 | fixed alu bugs | Flavian Kaufmann |
| 2024-05-01 | generate alu tests | Flavian Kaufmann |
| 2024-05-01 | alu | Flavian Kaufmann |
| 2024-04-27 | added README | Flavian Kaufmann |
| 2024-04-27 | added clock divider | Flavian Kaufmann |
| 2024-04-27 | simulation | Flavian Kaufmann |
| 2024-04-27 | initial commit | Flavian Kaufmann |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |