alu

4 files changed, 106 insertions, 0 deletions

diff --git a/src/alu.v b/src/alu.v
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+++ b/src/alu.v
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+module alu #(
+  parameter N = 32
+)(
+  input [N-1:0] A, B,
+  input [3:0] OP, // OP[3:2] 00: ARITHMETIC, 01: LOGIC, 10: SHIFT 
+  output reg [N-1:0] RESULT,
+  output ZERO,
+  output OVERFLOW
+);
+
+wire [N-1:0] arithmetic_result, logic_result, shift_result;
+
+arithmetic_unit #(.N(N)) au (
+  .A(A),
+  .B(B),
+  .OP(OP[1:0]),
+  .RESULT(arithmetic_result),
+  .OVERFLOW(overflow)
+);
+
+logic_unit #(.N(N)) lu (
+  .A(A),
+  .B(B),
+  .OP(OP[1:0]),
+  .RESULT(logic_result)
+);
+
+shift_unit #(.N(N)) su (
+  .A(A),
+  .SHAMT(B[clog2(N):0]),
+  .OP(OP[1:0]),
+  .RESULT(shift_result)
+);
+
+always @ (*) begin
+  case (OP[3:2])
+    2'b00: RESULT <= arithmetic_result;
+    2'b01: RESULT <= logic_result;
+    2'b10: RESULT <= shift_result;
+  endcase
+end
+
+assign OVERFLOW = OP[3:2] == 2'b00 ? overflow : 0;
+
+assign ZERO = ~|RESULT;
+
+endmodule
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v
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+++ b/src/arithmetic_unit.v
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+module arithmetic_unit #(
+  parameter N = 32
+)(
+  input [N-1:0] A, B,
+  input [1:0] OP, // 00: ADD, 01: SUB, 11: SLT
+  output [N-1:0] RESULT,
+  output OVERFLOW
+);
+
+wire [N-1:0] b, sum;
+wire cin, altb;
+
+assign b = OP[0] ? ~B : B;
+assign cin = OP[0];
+
+assign sum = A + b + cin;
+
+assign OVERFLOW = ~(A[N-1] ^ B[N-1] ^ OP[0]) & (A[N-1] ^ sum[N-1]);
+
+assign altb = OVERFLOW ^ sum[N-1];
+
+assign RESULT = OP[1] ? {{(N-1){1'b0}}, altb} : sum;
+
+endmodule
diff --git a/src/logic_unit.v b/src/logic_unit.v
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+++ b/src/logic_unit.v
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+module logic_unit #(
+  parameter N = 32
+)(
+  input [N-1:0] A, B,
+  input [1:0] OP, // 00: AND, 01: OR, 10: XOR
+  output reg [N-1:0] RESULT
+);
+  
+  always @ (*) begin
+    case (OP)
+      2'b00: RESULT <= A & B;
+      2'b01: RESULT <= A | B;
+      2'b10: RESULT <= A ^ B;
+    endcase
+  end
+
+endmodule
diff --git a/src/shift_unit.v b/src/shift_unit.v
new file mode 100644
index 0000000..55b6add
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+++ b/src/shift_unit.v
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+module shift_unit #(
+  parameter N = 32
+)(
+  input [N-1:0] A,
+  input [clog2(N):0] SHAMT,
+  input [1:0] OP, // 00: SLL, 01: SRL, 11: SRA 
+  output reg [N-1:0] RESULT
+);
+
+always @ (*) begin
+  case (OP)
+    2'b00: RESULT <= A << SHAMT;
+    2'b01: RESULT <= A >> SHAMT;
+    2'b11: RESULT <= A >>> SHAMT;
+  endcase
+end
+
+endmodule