simulation

3 files changed, 49 insertions, 10 deletions

diff --git a/Makefile b/Makefile
index 8a4049e..3714661 100644
--- a/Makefile
+++ b/Makefile
@@ -3,8 +3,10 @@ TOP_MODULE = top
 
 SRC_DIR = src
 CONSTRAINTS_DIR = constraints
+SIM_DIR = sim
 
 SOURCES = $(wildcard $(SRC_DIR)/*.v)
+TESTBENCH = $(SIM_DIR)/testbench.v
 CONSTRAINTS = $(CONSTRAINTS_DIR)/tangnano9k.cst
 
 BUILD_DIR = build
@@ -14,6 +16,9 @@ YOSYS = yosys
 NEXTPNR = nextpnr-gowin
 GOWIN_PACK = gowin_pack
 PROGRAMMER = openFPGALoader
+IVERILOG = iverilog
+VVP = vvp
+GTKWAVE = gtkwave
 
 FAMILY = GW1N-9C
 DEVICE = GW1NR-LV9QN88PC6/I5
@@ -49,8 +54,19 @@ program: $(BITSTREAM)
 flash: $(BITSTREAM)
 	$(PROGRAMMER) -b $(BOARD) -f $(BITSTREAM)
 
-
 clean:
 	rm -rf $(BUILD_DIR)
 
+simulate: $(BUILD_DIR)/testbench.vcd
+
+wave: $(BUILD_DIR)/testbench.vcd
+	$(GTKWAVE) $(BUILD_DIR)/testbench.vcd
+
+$(BUILD_DIR)/testbench: $(SOURCES) $(TESTBENCH)	
+	@mkdir -p $(BUILD_DIR)
+	$(IVERILOG) -o $(BUILD_DIR)/testbench $(SOURCES) $(TESTBENCH)
+
+$(BUILD_DIR)/testbench.vcd: $(BUILD_DIR)/testbench
+	cd $(BUILD_DIR); $(VVP) testbench
+
 .PHONY: all program clean
diff --git a/sim/testbench.v b/sim/testbench.v
new file mode 100644
index 0000000..6221b01
--- /dev/null
+++ b/sim/testbench.v
@@ -0,0 +1,26 @@
+module testbench;
+
+  reg reset = 0;
+  initial begin
+    $dumpfile("testbench.vcd");
+    $dumpvars(0,testbench);
+
+    # 17 reset = 1;
+    # 11 reset = 0;
+    # 29 reset = 1;
+    # 5  reset = 0;
+    # 128 $finish;
+  end
+
+  reg clk = 0;
+  always #1 clk = !clk;
+
+  wire [5:0] led;
+  wire reset_inv;
+  assign reset_inv = ~reset;
+  top blinky(.clk(clk), .key(reset_inv), .led(led));
+
+  initial
+     $monitor("At time %t, value = %h (%0d)", $time, led, led);
+
+endmodule
diff --git a/src/top.v b/src/top.v
index 8dc9684..6fab4a6 100644
--- a/src/top.v
+++ b/src/top.v
@@ -4,18 +4,15 @@ module top (
 	output [5:0] led
 );
 
-reg [25:0] ctr_q;
-wire [25:0] ctr_d;
+reg [5:0] ctr_q;
+wire [5:0] ctr_d;
 
-// Sequential code (flip-flop)
 always @(posedge clk) begin
-	if (key) begin
-		ctr_q <= ctr_d;
-	end
+	if (key) ctr_q <= ctr_d;
+	else ctr_q <= 6'b0;
 end
 
-// Combinational code (boolean logic)
-assign ctr_d = ctr_q + 1'b1;
-assign led = ctr_q[25:20];
+assign ctr_d = ctr_q + 6'b1;
+assign led = ctr_q;
 
 endmodule