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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-04-27 14:59:48 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-04-27 14:59:48 +0200 |
| commit | 1ee5fc13995ee1383b0b75a19003b08fe33cfa54 (patch) | |
| tree | 20ebcffaefde9cef161352f0485af35d1e232caa | |
| parent | 08d6eea4fc23e7f569bbfd883f0dc049272a4b47 (diff) | |
| download | riscv_cpu-1ee5fc13995ee1383b0b75a19003b08fe33cfa54.tar.gz riscv_cpu-1ee5fc13995ee1383b0b75a19003b08fe33cfa54.zip | |
added README
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | README.md | 12 |
2 files changed, 13 insertions, 1 deletions
@@ -69,4 +69,4 @@ $(BUILD_DIR)/testbench: $(SOURCES) $(TESTBENCH) $(BUILD_DIR)/testbench.vcd: $(BUILD_DIR)/testbench cd $(BUILD_DIR); $(VVP) testbench -.PHONY: all program clean +.PHONY: all program flash simulate wave clean diff --git a/README.md b/README.md new file mode 100644 index 0000000..b56e854 --- /dev/null +++ b/README.md @@ -0,0 +1,12 @@ +# RISCV CPU + +An attempt at building a simple RISCV CPU in verilog. + +## Build + +* `make all` to synthesize, place and route the design and to generate the bitstream. +* `make program` to upload the bitstream to the FPGA. +* `make flash` to flash the bitsream to the FPGA. +* `make simulate` to run the testbench (sim/testbench.v). +* `make wave` to view the simulation in GTKWave. +* `make clean` to clean build files. |