| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-21 | comments | Flavian Kaufmann |
| 2024-05-21 | restructured project | Flavian Kaufmann |
| 2024-05-20 | nextpnr himbaechel | Flavian Kaufmann |
| 2024-05-15 | running c program | Flavian Kaufmann |
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann |
| 2024-05-12 | refactoring | Flavian Kaufmann |
| 2024-05-09 | stopped initializing ram and register file to 0 at beginning | Flavian Kaufmann |
| 2024-05-09 | added remaining branch instructions | Flavian Kaufmann |
| 2024-05-08 | view cpu waveform with make wave | Flavian Kaufmann |
| 2024-05-08 | assemble simple rom | Flavian Kaufmann |
| 2024-05-07 | alu equal | Flavian Kaufmann |
| 2024-05-07 | cpu | Flavian Kaufmann |
| 2024-05-05 | genrom | Flavian Kaufmann |
| 2024-05-05 | added memory unit | Flavian Kaufmann |
| 2024-05-05 | register file testbench | Flavian Kaufmann |
| 2024-05-05 | added register file | Flavian Kaufmann |
| 2024-05-04 | renamed some signals | Flavian Kaufmann |
| 2024-05-04 | added support for multiple testbenches | Flavian Kaufmann |
| 2024-05-02 | cleaned test output | Flavian Kaufmann |
| 2024-05-01 | added make target for testvec generation | Flavian Kaufmann |
| 2024-05-01 | read alu_testvec.txt from tests/ | Flavian Kaufmann |
| 2024-05-01 | fixed alu bugs | Flavian Kaufmann |
| 2024-04-27 | simulation | Flavian Kaufmann |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |