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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-08 12:51:24 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-08 12:51:24 +0200 |
commit | 43d74babbfef9792f0f5fdd5ca13ec6ebf33655d (patch) | |
tree | 4c83522247c1ef2245222cd0cd47e307d4e8e1d7 /sim | |
parent | 4895d68fb533dc599b752936ef1dc8f5af80bc5a (diff) | |
download | riscv_cpu-43d74babbfef9792f0f5fdd5ca13ec6ebf33655d.tar.gz riscv_cpu-43d74babbfef9792f0f5fdd5ca13ec6ebf33655d.zip |
view cpu waveform with make wave
Diffstat (limited to 'sim')
-rw-r--r-- | sim/testbench_cpu.v | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v index ab3b31d..2a2e185 100644 --- a/sim/testbench_cpu.v +++ b/sim/testbench_cpu.v @@ -12,7 +12,7 @@ cpu uut ( integer file, r, eof; reg [100*8:1] line; -reg [31:0] test_count, error_count; +reg [31:0] clk_cycle_count; always #5 clk = ~clk; @@ -44,8 +44,7 @@ initial begin clk = 0; rst = 0; - test_count = 0; - error_count = 0; + clk_cycle_count = 0; @(negedge clk); rst = 1; @@ -55,8 +54,8 @@ initial begin while (1) begin @(posedge clk); - test_count = test_count + 1; - if (test_count == 100) $finish; + clk_cycle_count = clk_cycle_count + 1; + if (clk_cycle_count == 100) $finish; end end |