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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:13:51 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:13:51 +0200 |
| commit | 62fec7789b516561903358a29b45bd4a6746861f (patch) | |
| tree | 31b251ebdae1ba822619420cdfa7494252e16c01 /sim | |
| parent | ca5a25cfbdbefada9dfb94a097b65e69226f3f9a (diff) | |
| download | riscv_cpu-62fec7789b516561903358a29b45bd4a6746861f.tar.gz riscv_cpu-62fec7789b516561903358a29b45bd4a6746861f.zip | |
read alu_testvec.txt from tests/
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/testbench.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/testbench.v b/sim/testbench.v index 5a47111..33362d7 100644 --- a/sim/testbench.v +++ b/sim/testbench.v @@ -25,7 +25,7 @@ module testbench(); reg [103:0] testvec [0:9999]; initial begin - $readmemh("alu_testvec.txt", testvec); + $readmemh("../testvecs/alu_testvec.txt", testvec); error_count = 0; vector_count = 0; end |