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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-20 11:39:26 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-20 11:39:26 +0200 |
| commit | 407a3ff54a35cbe99ba6ac743376e9b0e9718fc1 (patch) | |
| tree | b96527b0b55bb63e21551f9a93d3c3271dd39988 /sim | |
| parent | def3f62f7f8d6b5bd4b15500c7d11935540e81da (diff) | |
| download | riscv_cpu-407a3ff54a35cbe99ba6ac743376e9b0e9718fc1.tar.gz riscv_cpu-407a3ff54a35cbe99ba6ac743376e9b0e9718fc1.zip | |
nextpnr himbaechel
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/testbench_cpu.v | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v index f227320..ba40dc2 100644 --- a/sim/testbench_cpu.v +++ b/sim/testbench_cpu.v @@ -5,10 +5,14 @@ module testbench_register_file(); reg clk; reg rst; +reg [31:0] io_in; +wire [31:0] io_out; + cpu cpu ( .clk(clk), .rstn(!rst), - .dbg_t6(_) + .io_in(io_in), + .io_out(io_out) ); integer file, r, eof; |