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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-05 14:37:31 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-05 14:37:31 +0200
commit5392b3d94038963a7121f391ad1b5075a5e32b8e (patch)
treec9f53d71a2837c78d919cceb76cbc922782c2088 /sim
parent1751c689d2005345b420d43584d7668c0ca93f6c (diff)
downloadriscv_cpu-5392b3d94038963a7121f391ad1b5075a5e32b8e.tar.gz
riscv_cpu-5392b3d94038963a7121f391ad1b5075a5e32b8e.zip
added memory unit
Diffstat (limited to 'sim')
-rw-r--r--sim/testbench_register_file.v12
1 files changed, 6 insertions, 6 deletions
diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v
index 093a624..07fa3e0 100644
--- a/sim/testbench_register_file.v
+++ b/sim/testbench_register_file.v
@@ -14,12 +14,12 @@ register_file uut (
.clk(clk),
.rst(rst),
.we(we),
- .addr_rs0(addr_rs0),
- .addr_rs1(addr_rs1),
- .addr_rd2(addr_rd2),
- .data_rs0(data_rs0),
- .data_rs1(data_rs1),
- .data_rd2(data_rd2)
+ .addr_read0(addr_rs0),
+ .addr_read1(addr_rs1),
+ .addr_write2(addr_rd2),
+ .data_read0(data_rs0),
+ .data_read1(data_rs1),
+ .data_write2(data_rd2)
);
integer file, r, eof;