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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 18:30:51 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 18:30:51 +0200 |
| commit | f6a55d5faba42120aa900e2514d9ff5d80dfca8b (patch) | |
| tree | c03fd620359c72402876ddb4708663166599b390 /sim | |
| parent | 14e5e2120e1176ce63f73adddd102934144c0f12 (diff) | |
| download | riscv_cpu-f6a55d5faba42120aa900e2514d9ff5d80dfca8b.tar.gz riscv_cpu-f6a55d5faba42120aa900e2514d9ff5d80dfca8b.zip | |
renamed some signals
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/testbench_alu.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/sim/testbench_alu.v b/sim/testbench_alu.v index 7d67d5c..068efc3 100644 --- a/sim/testbench_alu.v +++ b/sim/testbench_alu.v @@ -76,11 +76,11 @@ module testbench_alu(); alu #(.N(32)) alu ( - .A(a), - .B(b), - .OP(op), - .RESULT(result), - .ZERO(zero) + .alu_src0(a), + .alu_src1(b), + .alu_op(op), + .alu_result(result), + .alu_zero(zero) ); endmodule |