diff options
| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
| commit | 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (patch) | |
| tree | b8831bc5ad48d3375a5b05d6d532e2b3e0f2e490 /sim | |
| parent | deb7d0a6fc76d5250c238d479cf97d4755abef01 (diff) | |
| download | riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.tar.gz riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.zip | |
refactoring, runs now on fpga
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/testbench_cpu.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v index d6c3975..87b34d2 100644 --- a/sim/testbench_cpu.v +++ b/sim/testbench_cpu.v @@ -7,7 +7,8 @@ reg rst; cpu cpu ( .clk(clk), - .rstn(!rst) + .rstn(!rst), + .dbg_t6(_) ); integer file, r, eof; @@ -55,7 +56,7 @@ initial begin while (1) begin @(posedge clk); clk_cycle_count = clk_cycle_count + 1; - if (clk_cycle_count == 100) $finish; + if (clk_cycle_count == 1000) $finish; end end |