| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-21 | comments | Flavian Kaufmann |
| 2024-05-21 | test prog | Flavian Kaufmann |
| 2024-05-21 | restructured project | Flavian Kaufmann |
| 2024-05-21 | alu graphic | Flavian Kaufmann |
| 2024-05-21 | updated README | Flavian Kaufmann |
| 2024-05-21 | mixed up riscv tables in README | Flavian Kaufmann |
| 2024-05-21 | rv32 documentation | Flavian Kaufmann |
| 2024-05-21 | cleaned up graphics | Flavian Kaufmann |
| 2024-05-20 | fixed typo | Flavian Kaufmann |
| 2024-05-20 | added some graphics | Flavian Kaufmann |
| 2024-05-13 | async reset | Flavian Kaufmann |
| 2024-05-09 | added remaining branch instructions | Flavian Kaufmann |
| 2024-05-09 | fixed sw bug, where we wasn't set correctly | Flavian Kaufmann |
| 2024-05-08 | added references | Flavian Kaufmann |
| 2024-05-08 | Updated Readme with tool information | Flavian Kaufmann |
| 2024-05-08 | waveform example | Flavian Kaufmann |
| 2024-05-08 | view cpu waveform with make wave | Flavian Kaufmann |
| 2024-05-08 | updated readme for make rom | Flavian Kaufmann |
| 2024-05-05 | added info to view waveform with gtkwave to readme | Flavian Kaufmann |
| 2024-05-04 | renamed some signals | Flavian Kaufmann |
| 2024-05-04 | updated README.md for new Makefile | Flavian Kaufmann |
| 2024-05-01 | added make target for testvec generation | Flavian Kaufmann |
| 2024-04-27 | added README | Flavian Kaufmann |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |