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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 07:28:34 +0200 |
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| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 07:28:34 +0200 |
| commit | 9f1ab1f834c58c231617f3be12f16793061d4630 (patch) | |
| tree | dfb5040d4568010ecc765dee61f1ade9a4d7fc02 /README.md | |
| parent | 5a549e61af1df0c4016f00af830120d21a88a0e7 (diff) | |
| download | riscv_cpu-9f1ab1f834c58c231617f3be12f16793061d4630.tar.gz riscv_cpu-9f1ab1f834c58c231617f3be12f16793061d4630.zip | |
cleaned up graphics
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 9 |
1 files changed, 8 insertions, 1 deletions
@@ -61,12 +61,19 @@ The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardw * [Example RISCV Cores](https://github.com/yunchenlo/awesome-RISCV-Cores) ## Design -### Microarchitecture + +### Microarchitecture (RISC-V multicycle rv32i without ECALL/EBREAK) +  + ### Control Unit FSM +  + ### Memory Layout +  + ## Waveform Example Here we can see the waveforms of various internal signal of the CPU, executing the following instructions: |