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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-08 12:14:49 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-08 12:14:49 +0200 |
| commit | 4895d68fb533dc599b752936ef1dc8f5af80bc5a (patch) | |
| tree | 4b649a4d8c7217f5d7d5ce4684b1d72a2c18c16d /README.md | |
| parent | 7ff0d605067d57f638da50e53eb4a7dbb7ef11e6 (diff) | |
| download | riscv_cpu-4895d68fb533dc599b752936ef1dc8f5af80bc5a.tar.gz riscv_cpu-4895d68fb533dc599b752936ef1dc8f5af80bc5a.zip | |
updated readme for make rom
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -11,8 +11,9 @@ The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardw * `make all` alias for `make simulate`. * `make simulate` to run all the testbenches (sim/testbench_*.v). * `make bitstream` to synthesize, place and route the design and to generate the bitstream. -* `make program` to upload the bitstream to the FPGA. +* `make upload` to upload the bitstream to the FPGA. * `make flash` to flash the bitsream to the FPGA. * `make clean` to clean build files. * `gtkwave build/waveform_*.vcd` to view waveform of corresponding testbench. +* `make rom` to compile source files in prog/src, link and generate rom file. |