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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 18:30:51 +0200 |
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| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 18:30:51 +0200 |
| commit | f6a55d5faba42120aa900e2514d9ff5d80dfca8b (patch) | |
| tree | c03fd620359c72402876ddb4708663166599b390 /README.md | |
| parent | 14e5e2120e1176ce63f73adddd102934144c0f12 (diff) | |
| download | riscv_cpu-f6a55d5faba42120aa900e2514d9ff5d80dfca8b.tar.gz riscv_cpu-f6a55d5faba42120aa900e2514d9ff5d80dfca8b.zip | |
renamed some signals
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -2,6 +2,10 @@ An attempt at building a simple RISCV CPU in verilog. +## FPGA + +The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html) with a GW1NR-LV9QN88PC6/I5 FPGA. There is a crystal clock onboard running at 27 MHz. + ## Build * `make all` alias for `make simulate`. @@ -10,3 +14,4 @@ An attempt at building a simple RISCV CPU in verilog. * `make program` to upload the bitstream to the FPGA. * `make flash` to flash the bitsream to the FPGA. * `make clean` to clean build files. + |