added make target for testvec generation

1 files changed, 1 insertions, 0 deletions

diff --git a/README.md b/README.md
index b56e854..92f2fe0 100644
--- a/README.md
+++ b/README.md
@@ -7,6 +7,7 @@ An attempt at building a simple RISCV CPU in verilog.
 * `make all` to synthesize, place and route the design and to generate the bitstream.
 * `make program` to upload the bitstream to the FPGA.
 * `make flash` to flash the bitsream to the FPGA.
+* `make tests` to generate testvec files
 * `make simulate` to run the testbench (sim/testbench.v).
 * `make wave` to view the simulation in GTKWave.
 * `make clean` to clean build files.