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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-15 08:27:12 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-15 08:27:12 +0200 |
commit | 9e76b9001c37ab2da2e99c922406b991bd0e53af (patch) | |
tree | 686aa90639b28c92013e6158e01d5010973b0f03 /src/ram.v | |
parent | d107f7e40f02a7374b8685ba310500a6c38d43b1 (diff) | |
download | riscv_cpu-9e76b9001c37ab2da2e99c922406b991bd0e53af.tar.gz riscv_cpu-9e76b9001c37ab2da2e99c922406b991bd0e53af.zip |
running c program
Diffstat (limited to 'src/ram.v')
-rw-r--r-- | src/ram.v | 17 |
1 files changed, 7 insertions, 10 deletions
@@ -3,24 +3,21 @@ module ram #( parameter SIZE = 1024 )( input clk, - input rst, + input rstn, input we, - input [log2(SIZE)-1:0] addr, + input [log2(SIZE/4)-1:0] addr, input [N-1:0] data_write, - output [N-1:0] data_read + output reg [N-1:0] data_read ); `include "include/log2.vh" -reg [8:0] memory [SIZE-1:0]; - -assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] }; - +//(* RAM_STYLE="BLOCK" *) +reg [N-1:0] mem [SIZE-1:0]; always @(posedge clk) begin - if (we) begin - { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } <= data_write; - end + if (we) mem[addr >> 2] <= data_write; + data_read <= mem[addr >> 2]; end endmodule |