running c program

4 files changed, 18 insertions, 20 deletions

diff --git a/src/control_unit.v b/src/control_unit.v
index dfed9cc..28f37d9 100644
--- a/src/control_unit.v
+++ b/src/control_unit.v
@@ -104,7 +104,7 @@ always @ (*) begin
     STATE_JAL:       next_state = STATE_ALU_WB;
     STATE_JALR:      next_state = STATE_ALU_WB;
     STATE_LUI:       next_state = STATE_ALU_WB;
-    STATE_AUIPC:     next_state = STATE_FETCH;
+    STATE_AUIPC:     next_state = STATE_ALU_WB;
     STATE_BRANCH:    next_state = STATE_FETCH;
     default:         next_state = STATE_FETCH; 
   endcase
@@ -193,9 +193,6 @@ always @ (*) begin
       alu_a_src    = ALU_A_SRC_PC_BUF;
       alu_b_src    = ALU_B_SRC_IMM;
       alu_ctrl     = ALU_CTRL_ADD;
-      result_src   = RESULT_SRC_ALU_RESULT_BUF;
-      pc_update    = PC_UPDATE_ENABLE;
-
     end
     STATE_BRANCH: begin
       alu_a_src    = ALU_A_SRC_RD1_BUF;
diff --git a/src/memory_interface.v b/src/memory_interface.v
index 0fabc05..da06d1a 100644
--- a/src/memory_interface.v
+++ b/src/memory_interface.v
@@ -14,7 +14,7 @@ wire [31:0] ram_read_data, rom_read_data;
 
 ram #(.N(32), .SIZE(1024)) ram(
   .clk(clk),
-  .rst(!rstn),
+  .rstn(rstn),
   .we(ram_we),
   .addr(addr),
   .data_read(ram_read_data),
diff --git a/src/ram.v b/src/ram.v
index 3e5783d..91bb133 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -3,24 +3,21 @@ module ram #(
   parameter SIZE = 1024
 )(
     input clk,
-    input rst,
+    input rstn,
     input we,
-    input [log2(SIZE)-1:0] addr,
+    input [log2(SIZE/4)-1:0] addr,
     input [N-1:0] data_write,
-    output [N-1:0] data_read
+    output reg [N-1:0] data_read
 );
 
 `include "include/log2.vh"
 
-reg [8:0] memory [SIZE-1:0];
-
-assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
-
+//(* RAM_STYLE="BLOCK" *)
+reg [N-1:0] mem [SIZE-1:0];
 
 always @(posedge clk) begin
-  if (we) begin
-    { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } <= data_write;
-  end
+  if (we) mem[addr >> 2] <= data_write; 
+  data_read <= mem[addr >> 2];
 end
 
 endmodule
diff --git a/src/rom.v b/src/rom.v
index 381ca64..b317094 100644
--- a/src/rom.v
+++ b/src/rom.v
@@ -3,18 +3,22 @@ module rom #(
   parameter SIZE = 1024
 )(
     input clk,
-    input [log2(SIZE)-1:0] addr,
-    output [N-1:0] data_read
+    input [log2(SIZE/4)-1:0] addr,
+    output reg [N-1:0] data_read
 );
 
 `include "include/log2.vh"
 
-reg [7:0] memory [0:SIZE-1];
+
+//(* RAM_STYLE="BLOCK" *)
+reg [N-1:0] mem [SIZE-1:0];
 
 initial begin
-  $readmemh("build/rom.hex", memory, 0, SIZE-1);
+  $readmemh("build/rom.hex", mem, 0, SIZE/4-1);
 end
 
-assign data_read = {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
+always @(negedge clk) begin
+  data_read <= mem[addr >> 2];
+end
 
 endmodule