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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-14 10:38:47 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-14 10:38:47 +0200
commitd107f7e40f02a7374b8685ba310500a6c38d43b1 (patch)
tree55615eaface31b2473be3dae90fe822c5373f492 /src/ram.v
parent48b36fddef862c3cd5efbdd3ed3e86b179ac117b (diff)
downloadriscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.tar.gz
riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.zip
bug fixes
Diffstat (limited to 'src/ram.v')
-rw-r--r--src/ram.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/ram.v b/src/ram.v
index 8234d5d..3e5783d 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -19,7 +19,7 @@ assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memor
always @(posedge clk) begin
if (we) begin
- { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
+ { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } <= data_write;
end
end