1 files changed, 22 insertions, 20 deletions
diff --git a/src/clock_divider.v b/src/clock_divider.v
index 499d8b2..0ece86d 100644
--- a/src/clock_divider.v
+++ b/src/clock_divider.v
@@ -1,27 +1,29 @@
 module clock_divider #( 
-    parameter N = 2
+  parameter N = 2
 )(
-    input clk,
-    input reset,
-    output reg clk_out
+  input clk,
+  input rstn,
+
+  output reg clk_div
 );
 
-    reg [31:0] counter = 0;
+reg [31:0] counter = 0;
 
-    always @(posedge clk or posedge reset) begin
-        if (reset) begin
-            counter <= 0;
-            clk_out <= 0;
-        end else begin
-            if (counter == (N-1)/2) begin
-                clk_out <= ~clk_out;
-                counter <= counter + 1;
-            end else if (counter >= (N-1)) begin
-                clk_out <= ~clk_out;
-                counter <= 0;
-            end else begin
-                counter <= counter + 1;
-            end
-        end
+always @(posedge clk) begin
+  if (!rstn) begin
+    counter <= 0;
+    clk_div <= 0;
+  end else begin
+    if (counter == (N-1)/2) begin
+      clk_div <= ~clk_div;
+      counter <= counter + 1;
+    end else if (counter >= (N-1)) begin
+      clk_div <= ~clk_div;
+      counter <= 0;
+    end else begin
+      counter <= counter + 1;
     end
+  end
+end
+
 endmodule